An area-optimality study of floorplanning

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2004, Pages 78-83

  Cong, Jason ^a   Nataneli, Gabriele ^a   Romesis, Michail ^a   Shinnerl, Joseph R ^a  

^a Engineering IV   (United States)

Author keywords

Area Partitioning; Aspect Ratios; Benchmarking; Block Packing; Floorplanning; Optimality; Placement

Indexed keywords

AGGLOMERATION; ALGORITHMS; ASPECT RATIO; BENCHMARKING; PERTURBATION TECHNIQUES; SEMICONDUCTOR MATERIALS;

AREA PARTITIONING; BLOCK PACKING; FLOORPLANNING;

VLSI CIRCUITS;

EID: 2942672238     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/981066.981083     Document Type: Conference Paper

References (23)

1. S. Adya and I. Markov. Fixed-outline floorplanning through better local search. In Proc. International Conference on Computer Design, pages 328-334, 2001.
2. http://vlsicad.eecs.umich.edu/bk/blobb.
3. http://cc.ee.ntu.edu.tw/~ywchang/research.html.
4. H. Chan and I. Markov. Symmetries in rectangular block-packing. In Proc. of the International Workshop on Symmetry in Constraint Satisfaction Problems, Sep. 2003.
5. C.C. Chang, J. Gong, and M. Xie. Optimality and scalability study of existing placement algorithms. In Asia South Pacific Design Automation Conference, pages 325-330, Kitakyushu, Japan, Jan 2003.
6. Y.C. Chang, Y.W. Chang, G. Wu, and S. Wu. B*-trees: A new representation for non-slicing floorplans. In Proc. Design Automation Conference, pages 458-463, 2000.
7. J. Cong, M. Romesis, and M. Xie. Optimality, stability and scalability study of partitioning and placement algorithms. In Proc. of the International Symposium on Physical Design, pages 89-94, 2003.
8. http://www.cse.ucsc.edu/research/surf/GSRC/GSRCbench.html.
9. P. Guo, C. Cheng, and T. Yoshimura. An O-tree representation of non-slicing floorplan and its applications. In Proc. Design Automation Conference, pages 328-334, 1999.
10. X. Hong, S. Dong, G. Huang, Y. Ma, Y. Cai, C. Cheng, and J. Gu. A non-slicing floorplanning algorithm using corner block list topological representation. In Proc. Design Automation Conference, pages 268-273, 1999.
11. J. Lin and Y. Chang. TCG: A transitive closure graph-based representation for non-slicing floorplans. In Proc. Design Automation Conference, pages 764-769, 2001.
12. J. Lin and Y. Chang. TCG-S: Orthogonal coupling of P*-admissible representations for general floorplans. In Proceedings of the Design Automation Conference, pages 842-847, 2002.
13. http://www.cse.ucsc.edu/research/surf/GSRC/MCNCbench.html.
14. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. Rectangle-packing-based module placement. In Proc. International Conference on Computer-Aided Design, pages 472-479, 1995.
15. S. Nakatake, K. Fujiyoshi, H. Mirata, and Y. Kajitani. Module packing based on the BSG-structure and IC layout applications. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systesms, volume 17, pages 519-530, 1998.
16. T. Okamoto and T. Yoshimura. A new approach to VLSI floorplanning based on quadratic programming and rectangle packing. In Proc. of the 10th Workshop on Synthesis and System Integration of Mixed Technologies, 2001.
17. R. Otten. Automatic floorplan design. In Proc. Design Automation Conference, pages 261-267, 1982.
18. http://vlsicad.eecs.umich.edu/bk/parquet/.
19. H. Peixoto, M. Jacome, A. Royo, and J. Lopez. A tight upper bound for slicing floorplans. In Proc. of IEEE VLSI 2000, Jan. 2000.
20. J. Shinnerl. A theorem on partitioning a sorted list of numbers with an application to VLSI floorplanning. Report 040006, Computer Science Dept., University of California, Los Angeles, http://www.cs.ucla.edu/~shinnerl, Feb. 2004.
21. D.F. Wong and C.L. Liu. A new algorithm for floorplan design. In Proc. Design Automation Conference, pages 101-107, 1986.
22. http://cadlab.cs.ucla.edu/~pubbench/floor.
23. F. Young and D. Wong. How good are slicing floorplans? In Proc. of the International Symposium on Physical Design, pages 144-149, 1997.