-
1
-
-
0031652243
-
Faster minimization of linear wirelength for global placement
-
C. J. Alpert, T. Chan, A. B. Kahng, I. Markov and P. Mulet, "Faster Minimization of Linear Wirelength for Global Placement", IEEE Trans. Computer Aided Design 17(1) (1998), pp. 3-13.
-
(1998)
IEEE Trans. Computer Aided Design
, vol.17
, Issue.1
, pp. 3-13
-
-
Alpert, C.J.1
Chan, T.2
Kahng, A.B.3
Markov, I.4
Mulet, P.5
-
3
-
-
0009790428
-
Function smoothing with applications to VLSI layout
-
Jan.
-
R. Baldick, A. B. Kahng, A. Kennings and I. L. Markov, "Function Smoothing with Applications to VLSI Layout", Proc. IEEE/ACM Asia and South Pacific Design Automation Conf., Jan. 1999, pp. 225-228.
-
(1999)
Proc. IEEE/ACM Asia and South Pacific Design Automation Conf.
, pp. 225-228
-
-
Baldick, R.1
Kahng, A.B.2
Kennings, A.3
Markov, I.L.4
-
4
-
-
0033697586
-
Can recursive bisection alone produce routable placements?
-
A. E. Caldwell, A. B. Kahng, and I. L. Markov, "Can Recursive Bisection Alone Produce Routable Placements?", Proc. ACM/IEEE Design Automation Conf., 2000, pp. 477-482.
-
(2000)
Proc. ACM/IEEE Design Automation Conf.
, pp. 477-482
-
-
Caldwell, A.E.1
Kahng, A.B.2
Markov, I.L.3
-
5
-
-
0032651060
-
Hypergraph partitioning for VLSI CAD: Methodology for reporting, and new results
-
June
-
A. E. Caldwell, A. B. Kahng, A. A. Kennings and I. L. Markov, "Hypergraph Partitioning for VLSI CAD: Methodology for Reporting, and New Results", Proc. ACM/IEEE Design Automation Conf., June 1999, pp. 349-354.
-
(1999)
Proc. ACM/IEEE Design Automation Conf.
, pp. 349-354
-
-
Caldwell, A.E.1
Kahng, A.B.2
Kennings, A.A.3
Markov, I.L.4
-
6
-
-
84886477330
-
Implications of area-array I/O for row-based placement methodology
-
Feb.
-
A. E. Caldwell, A. B. Kahng, S. Mantik and I. L. Markov, "Implications of Area-Array I/O for Row-Based Placement Methodology", Proc. IEEE Symp. IC/Package Design Integration, Feb. 1998, pp. 93-98.
-
(1998)
Proc. IEEE Symp. IC/Package Design Integration
, pp. 93-98
-
-
Caldwell, A.E.1
Kahng, A.B.2
Mantik, S.3
Markov, I.L.4
-
10
-
-
84862356924
-
ARP: A convex optimization based method for global placement
-
submitted to
-
H. Etawil, S. Areibi and A. Vannelli, "ARP: A Convex Optimization Based Method for Global Placement", submitted to IEEE Trans. Computer Aided Design, http://wolfman.eos.uoguelph.ca/~sareibi1/ PUBLICATIONS_dr/all-pub-list. html.
-
IEEE Trans. Computer Aided Design
-
-
Etawil, H.1
Areibi, S.2
Vannelli, A.3
-
12
-
-
0027872967
-
A performance driven hierarchical partitioning placement algorithm
-
Sep.
-
T. Gao, C. L. Liu and K. C. Chen, "A Performance Driven Hierarchical Partitioning Placement Algorithm", Proc. European Design Automation Conf., Sep. 1993, pp. 33-38.
-
(1993)
Proc. European Design Automation Conf.
, pp. 33-38
-
-
Gao, T.1
Liu, C.L.2
Chen, K.C.3
-
13
-
-
84862356487
-
-
"Method and System for High Speed Detailed Placement of Cells within an Integrated Circuit Design", US Patent 6370673, April
-
D. Hill, "Method and System for High Speed Detailed Placement of Cells within an Integrated Circuit Design", US Patent 6370673, April 2002.
-
(2002)
-
-
Hill, D.1
-
14
-
-
0030646008
-
Partitioning-based standard cell global placement with an exact objective
-
D. J. Huang and A. B. Kahng, "Partitioning-Based Standard Cell Global Placement With an Exact Objective", Proc. Int. Symp. Physical Design, 1997, pp. 18-25.
-
(1997)
Proc. Int. Symp. Physical Design
, pp. 18-25
-
-
Huang, D.J.1
Kahng, A.B.2
-
18
-
-
0030686036
-
Multilevel hypergraph partitioning: Applications in VLSI design
-
G. Karypis, R. Aggarwal, V. Kumar and S. Shekhar, "Multilevel Hypergraph Partitioning: Applications in VLSI Design", Proc. ACM/IEEE Design Automation Conf., 1997, pp. 526-529.
-
(1997)
Proc. ACM/IEEE Design Automation Conf.
, pp. 526-529
-
-
Karypis, G.1
Aggarwal, R.2
Kumar, V.3
Shekhar, S.4
-
19
-
-
0036311655
-
Smoothening max-terms and analytical minimization of half-perimeter wirelength
-
A. A. Kennings and I. L. Markov, "Smoothening Max-terms and Analytical Minimization of Half-Perimeter Wirelength", VLSI Design 14(3) (2002), pp. 229-237.
-
(2002)
VLSI Design
, vol.14
, Issue.3
, pp. 229-237
-
-
Kennings, A.A.1
Markov, I.L.2
-
21
-
-
0026131224
-
GORDIAN: VLSI placement by quadratic programming and slicing optimization
-
J. Kleinhans, G. Sigl, F. Johannes and K. Antreich, "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization", IEEE Trans. Computer-Aided Design 10(3) (1991), pp. 356-365.
-
(1991)
IEEE Trans. Computer-aided Design
, vol.10
, Issue.3
, pp. 356-365
-
-
Kleinhans, J.1
Sigl, G.2
Johannes, F.3
Antreich, K.4
-
22
-
-
2942683893
-
-
private communication, Oct.
-
C.-K. Koh and C. Li, private communication, Oct. 2003.
-
(2003)
-
-
Koh, C.-K.1
Li, C.2
-
23
-
-
0029695151
-
New spectral linear placement and clustering approach
-
J.-M. Li, J. Lillis, L.-T. Liu and C.-K. Cheng, "New Spectral Linear Placement and Clustering Approach", Proc. ACM/IEEE Design Automation Conf., 1996, pp. 88-93.
-
(1996)
Proc. ACM/IEEE Design Automation Conf.
, pp. 88-93
-
-
Li, J.-M.1
Lillis, J.2
Liu, L.-T.3
Cheng, C.-K.4
-
26
-
-
84862359933
-
-
Non-Linear Optimization System and Method for Wire Length and Delay Optimization for an Automatic Electric Circuit Placer", US Patent 6301693, Oct.
-
W. Naylor et al., "Non-Linear Optimization System and Method for Wire Length and Delay Optimization for an Automatic Electric Circuit Placer", US Patent 6301693, Oct. 2001.
-
(2001)
-
-
Naylor, W.1
-
29
-
-
0029264395
-
Efficient and effective placement for very large circuits
-
W.-J. Sun and C. Sechen, "Efficient and Effective Placement for Very Large Circuits", IEEE Trans. Computer-Aided Design 14(3) (1995), pp. 349-359.
-
(1995)
IEEE Trans. Computer-aided Design
, vol.14
, Issue.3
, pp. 349-359
-
-
Sun, W.-J.1
Sechen, C.2
-
31
-
-
0024890267
-
IBM RISC chip design methodology
-
P. Villarrubia, G. Nusbaum, R. Masleid and P. T. Patel, "IBM RISC Chip Design Methodology", Proc. Int. Conf. Computer Design , 1989, pp. 143-147.
-
(1989)
Proc. Int. Conf. Computer Design
, pp. 143-147
-
-
Villarrubia, P.1
Nusbaum, G.2
Masleid, R.3
Patel, P.T.4
-
34
-
-
0036375950
-
Routability driven white space allocation for fixed-die standard-cell placement
-
X. Yang, B.-K. Choi and M. Sarrafzadeh, "Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement", Proc. Int. Symp. Physical Design, 2002, pp. 42-47.
-
(2002)
Proc. Int. Symp. Physical Design
, pp. 42-47
-
-
Yang, X.1
Choi, B.-K.2
Sarrafzadeh, M.3
|