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Volumn , Issue , 2000, Pages 458-463

B*-trees: A new representation for non-slicing floorplans

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; DATA STRUCTURES; ELECTRIC NETWORK TOPOLOGY; SEMICONDUCTING SILICON; SIMULATED ANNEALING;

EID: 0033701594     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2000.855354     Document Type: Article
Times cited : (488)

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  • 2
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    • Arbitrary Rectilinear Block Packing Based on Sequence Pair
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    • (1998) , pp. 259-266
    • Kang, M.Z.1    Dai, W.2
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    • Optimization by Simulated Annealing
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    • (1983) Science , vol.220 , Issue.4598 , pp. 671-680
    • Kirkpatrick, S.1    Gelatt, C.D.2    Vecchi, M.P.3
  • 5
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    • T. C. Lee An Bounded 2D Contour Searching Algorithm for Floorplan Design with Arbitrarily Shaped Rectilinear and Soft Modules Proc. DAC 525 530 Proc. DAC 1993
    • (1993) , pp. 525-530
    • Lee, T.C.1
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    • H. Murata K. Fujiyoshi S. Nakatake Y. Kajitani Rectangle-Packing Based Module Placement Proc. ICCAD 472 479 Proc. ICCAD 1995
    • (1995) , pp. 472-479
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    • H. Murata K. Fujiyoshi M. Kaneko VLSI/PCB Placement with Obstacles Based on Sequence Pair Proc. ISPD 26 31 Proc. ISPD 1997
    • (1997) , pp. 26-31
    • Murata, H.1    Fujiyoshi, K.2    Kaneko, M.3
  • 8
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    • H. Murata E. S. Kuh Sequence Pair Based Placement Method for Hard/Soft/Pre-placed Modules Proc. ISPD 167 172 Proc. ISPD 1998
    • (1998) , pp. 167-172
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  • 9
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.