An Enhanced Multilevel Algorithm for Circuit Placement

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 299-306

  Chan, Tony F ^b   Cong, Jason ^a   Kong, Tim ^c   Shinnerl, Joseph R ^a   Sze, Kenton ^b  

^a University of California   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c MAGMA DESIGN AUTOMATION   (United States)

Author keywords

Algebraic Multigrid (AMG); Multilevel Optimization; Placement; Quadratic Programming (QP)

Indexed keywords

ALGEBRA; ALGORITHMS; APPROXIMATION THEORY; COMPUTER AIDED DESIGN; INTERPOLATION; ITERATIVE METHODS; LINEAR SYSTEMS; OPTIMIZATION; PARTIAL DIFFERENTIAL EQUATIONS; QUADRATIC PROGRAMMING; SET THEORY;

ALGEBRAIC MULTIGRID (AMG); MULTILEVEL PLACERS;

VLSI CIRCUITS;

EID: 0347409202     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159704     Document Type: Conference Paper

References (32)

1. C. Alpert, J.-H. Huang, and A. Kahng. Multilevel circuit partitioning. In Proc. 34th IEEE/ACM Design Automation Conf., 1997.
2. C. J. Alpert. The ISPD98 circuit benchmark suite. In Proc. Intl Symposium on Physical Design, pages 80-85, 1998.
3. A. Brandt. Multi-level adaptive solutions to boundary value problems. Mathematics of Computation, 31(138):333-390, 1977.
4. A. Brandt. Algebraic multigrid theory: The symmetric case. Appl. Math. Comp., 19:23-56, 1986.
5. A. Brandt. Multiscale scientific computation: Review 2001. In T. Barth, R. Haimes, and T. Chan, editors, Multiscale and Multiresolution Methods. Springer Verlag, 2001.
6. A. Brandt and D. Ron. Multigrid Solvers and Multilevel Optimization Strategies, chapter 1 of Multilevel Optimization and VLSICAD. Kluwer Academic Publishers, Boston, 2002.
7. U. Brenner and A. Rohe. An effective congestion-driven placement framework. In Proc. International Symposium on Physical Design, Apr 2002.
8. W. L. Briggs, S. F. McCormick, and V. E. Henson. A Multigrid Tutorial. SIAM, Philadelphia, second edition, 2000.
9. A. Caldwell, A.B.Kahng, and I. Markov. Improved algorithms for hypergraph partitioning. In Proc. IEEE/ACM Asia South Pacific Design Automation Conf., 2000.
10. A. Caldwell, A. Kahng, and I. Markov. Can recursive bisection alone produce routable placements? In Proc. 37th IEEE/ACM Design Automation Conf., 2000.
11. T. Chan, J. Cong, T. Kong, and J. Shinnerl. Multilevel Circuit Placement, chapter 4 of Multilevel Optimization in VLSICAD. Kluwer Academic Publishers, Boston, 2003.
12. T. Chan, J. Cong, T. Kong, and J. Shinnerl. Multilevel optimization for large-scale circuit placement. In Proc. IEEE International Conference on Computer Aided Design, pages 171-176, San Jose, CA, Nov 2000.
13. C. Chang, J. Gong, Z. Pan, and X. Yuan. Physical hierarchy generation with routing congestion control. In Proc. ACM International Symposium on Physical Design, pages 36-41, San Diego, CA, Apr 2002.
14. C. Chang, J. Cong, and M. Xie. Optimality and scalability study of existing placement algorithms. In Asia South Pacific Design Automation Conference, pages 325-330, Kitakyushu, Japan, Jan 2003.
15. C.-C. Chang, J. Cong, D. Pan, and X. Yuan. Multilevel global placement with congestion control. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 22(4):395-409, April 2003.
16. J. Cong and S. Lim. Performance-driven multiway partitioning. In Proc. IEEE/ACM Asia South Pacific Design Automation Conf., 2000.
17. J. Cong and J. R. Shinnerl, editors. Multilevel Optimization in VLSICAD. Kluwer Academic Publishers, Boston, 2003.
18. K. Doll, F. Johannes, and K. Antreich. Iterative placement improvement by network flow methods. IEEE Transactions on Computer-Aided Design, 13(10), Oct 1994.
19. H. Eisenmann and F. M. Johannes. Generic global placement and floorplanning. In Proc. 35th ACM/IEEE Design Automation Conference, pages 269-274, 1998.
20. S. Goto. An efficient algorithm for the two-dimensional placement problem in electrical circuit layout. IEEE Trans. on Circuits and Systems, 28(1):12-18, January 1981.
21. S.-W. Hur and J. Lillis. Mongrel: Hybrid techniques for standard-cell placement. In Proc. IEEE International Conference on Computer Aided Design, pages 165-170, San Jose, CA, Nov 2000.
22. G. Karypis. Multilevel algorithms for multi-constraint hypergraph partitioning. Technical Report 99-034, Department of Computer Science, University of Minnesota, Minneapolis, 1999.
23. G. Karypis. Multilevel Hypergraph Partitioning, chapter 3 of Multilevel Optimization and VLSICAD. Kluwer Academic Publishers, Boston, 2002.
24. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph partitioning: Application in vlsi domain. In Proc. 34th ACM/IEEE Design Automation Conference, pages 526-529, 1997.
25. J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich. Gordian: Vlsi placement by quadratic programming and slicing optimization. IEEE Trans. on Computer-Aided Design, CAD-10:356-365, 1991.
26. T. Kong. A novel net weighting algorithm for timing-driven placement. In Proc. IEEE International Conference on Computer Aided Design, pages 172-176, 2002.
27. S. McCormick, editor. Multigrid Methods. SIAM, Philadelphia, 1987.
28. Y. Sankar and J. Rose. Trading quality for compile time: Ultra-fast placement for FPGAs. In FPGA '99, ACM Symp. on FPGAs, pages 157-166, 1999.
29. G. Sigl, K. Doll, and F. M. Johannes. Analytical placement: A linear or a quadratic objective function? In Proc. 28th ACM/IEEE Design Automation Conference, pages 427-432, 1991.
30. K. Stueben. A review of algebraic multigrid. Technical Report 69, GMD National Research Center for Information Technology, Bonn, 1999.
31. W.-J. Sun and C. Sechen. Efficient and effective placement for very large circuits. IEEE Trans. on Computer-Aided Design, pages 349-359, Mar 1995.
32. M. Wang, X. Yang, and M. Sarrafzadeh. Dragon2000: Fast standard-cell placement for large circuits. Proc. IEEE/ACM International Conference on Computer-Aided Design, pages 260-263, Apr 2000.