Optimal redistribution of white space for wire length minimization

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 412-417

  Tang, Xiaoping ^a   Tian, Ruiqi ^b   Wong, Martin D F ^c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; LINEAR PROGRAMMING; POLYNOMIAL APPROXIMATION;

BLOCK PLACEMENT; FIRST ORDER; FIXED FRAMES; FLOOR-PLANNING; POLYNOMIAL-TIME; TOTAL WIRE LENGTH; WHITE SPACE; WIRELENGTH MINIMIZATION;

WIRE;

EID: 54549110399     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120900     Document Type: Conference Paper

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