PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 41-48

  Wu, W ^a   Li, X ^a   Gildenblat, G ^a   Workman, G ^b   Veeraraghavan, S ^b   McAndrew, C ^c   Van Langevelde, R ^b   Smit, G D J ^d   Scholten, A J ^d   Klaassen, D B M ^d   Watts, J ^e  

^a Arizona State University   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

^d NXP SEMICONDUCTORS   (Netherlands)

^e IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; MOSFET DEVICES;

BODY RESISTANCE; FLOATING BODIES; INDUSTRY STANDARDS; PARTIALLY DEPLETED; PARTIALLY DEPLETED SOI MOSFETS; RECENT PROGRESS; SPECIFIC EFFECTS; SURFACE POTENTIAL-BASED;

SURFACE POTENTIAL;

EID: 57749209718     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405678     Document Type: Conference Paper

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