History-effect-conscious SPICE model extraction for PD-SOI technology

Proceedings - IEEE International SOI Conference

Volumn , Issue , 2004, Pages 156-158

  Goo, Jung Suk ^a   An, Judy Xilin ^a   Thuruthiyil, Ciby ^a   Ly, Tran ^a   Chen, Qiang ^a   Radwin, Martin ^a   Wu, Zhi Yuan ^a   Lee, Michael S L ^a   Zamudio, Luis ^a   Yonemura, James ^a   Assad, Farzin ^a   Pelella, Mario M ^a   Icel, Ali B ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FITTING GUIDELINES; HISTORY EFFECTS; PARTIAL DEPLETION; THIN BODY;

CARRIER CONCENTRATION; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA REDUCTION; DELAY CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; MOS DEVICES; SILICON ON INSULATOR TECHNOLOGY; SWITCHES; SWITCHING; VOLTAGE DIVIDERS;

ELECTRIC NETWORK ANALYSIS;

EID: 20144388822     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A. Wei and D. A. Antoniadis, "Bounding the Severity of Hysteretic Transient Effects in Partially-Depleted SOI CMOS," Proceedings of IEEE International SOI Conference, pp. 74-75, October 1996.
2. K. Bernstein and N. J. Rohrer, "SOI Circuit Design Concepts," Chapter 3, 1st Edition, 2000.
3. P. Su et al., Proc. of ISQED, pp. 487-491, 2002.
4. M. H. Na et al., Proc. of Nanotechnology Conference and Trade Show, Vol. 2, pp. 183-186, March 2004.