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Volumn 53, Issue 9, 2006, Pages 2202-2206

Validation of MOSFET model source-drain symmetry

Author keywords

Modeling; MOSFETs; SPICE

Indexed keywords

CIRCUIT SIMULATION; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SPICE;

EID: 33846100229     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.881005     Document Type: Article
Times cited : (106)

References (12)
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    • Sep
    • N. Scheinberg and A. Pinkhasov, "A computer simulation model for simulating distortion in FET resistors," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 9, pp. 981-989, Sep. 2000.
    • (2000) IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst , vol.19 , Issue.9 , pp. 981-989
    • Scheinberg, N.1    Pinkhasov, A.2
  • 4
    • 33947108192 scopus 로고
    • Murray Hill, NJ: AT&T Bell Laboratories, Oct. 30
    • _, Review of AUSSIM Model. Murray Hill, NJ: AT&T Bell Laboratories, Oct. 30, 1990.
    • (1990) Review of AUSSIM Model
    • Gummel, H.K.1
  • 6
    • 59849100043 scopus 로고
    • Benchmarks for compact MOSFET models
    • "Benchmarks for compact MOSFET models," in SEMATECH Compact Models Workshop, 1995.
    • (1995) SEMATECH Compact Models Workshop
  • 7
    • 33947104392 scopus 로고    scopus 로고
    • Available
    • [Online]. Available: http://ray.eeel.nist.gov/modval/database/contents/ reports/micromosfet/standard.htm
  • 9
    • 0029201727 scopus 로고
    • Benchmarking MOS transistor models with respect to capacitances and charges for analog applications
    • U. Feldmann, A. Rahm, and M. Miura-Mattausch, "Benchmarking MOS transistor models with respect to capacitances and charges for analog applications," in Proc. IEEE ISCAS, 1995, pp. 1352-1355.
    • (1995) Proc. IEEE ISCAS , pp. 1352-1355
    • Feldmann, U.1    Rahm, A.2    Miura-Mattausch, M.3
  • 10
    • 33947158957 scopus 로고    scopus 로고
    • Available
    • [Online]. Available: http://www-device.eecs.berkeley.edu/~bsim3/bsim4. html
  • 11
    • 0003742016 scopus 로고    scopus 로고
    • Analytical MOS transistor modelling for analog circuit simulation,
    • Ph.D. dissertation, EPFL, Swiss Federal Institute of Technology, Lausanne, Switzerland, No. 2114
    • M. Bucher, "Analytical MOS transistor modelling for analog circuit simulation," Ph.D. dissertation, EPFL, Swiss Federal Institute of Technology, Lausanne, Switzerland, 1999. No. 2114.
    • (1999)
    • Bucher, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.