SOI technology for the GHz era

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2001, Pages 11-14

  Shahidi, G G ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; PRINTED CIRCUIT DESIGN; STATIC RANDOM ACCESS STORAGE;

FLOATING BODY EFFECTS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0034842505     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. A room temperature 0.1 μm CMOS on SOI
2. A 0.25 μm CMOS on SOI and its application to 4 Mb SRAM
3. Non-fully-depleted SOI technology for digital logic
4. A 0.22 μm CMOS SOI technology
5. A 0.2 micron 1.8 V SOI 550 MHz 64b PowerPC microprocessor
6. A 580 MHz 32 bit PowerPC microprocessor in 0.12 micron leff CMOS SOI with Cu interconnects
7. 0.25 micron 1.8 V 1 GHz PLL for SOI microprocessors
8. A 0.18 μm CMOS on SOI technology
9. Scaling challenges and device design for the Sub-50 nm gate length planar CMOS transistors
10. Controlling floating-body effects for 0.13 and 0.1μm CMOS SOI
11. History-dependence of Non-Fully Depleted (NFD) digital SOI circuits
12. Transient pass-transistor leakage current in SOI MOSFET's
13. A 0.18 μm 1.5V SOI 660 MHz 64b PowerPC microprocessor with copper interconnects
14. nd generation 440 ps SOI 64b adder
15. Physical design of a forth- generation power GHz microprocessor
16. A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-K BEOL dielectric
17. SOI CMOS for low power and RF
18. 0.25 μm merged bulk DRAM and SOI logic using patterned SOI