A surface potential-based compact model of n-MOSFET gate-tunneling current

IEEE Transactions on Electron Devices

Volumn 51, Issue 1, 2004, Pages 127-135

  Gu, Xin Ben ^a   Chen, Ten Lon ^a   Gildenblat, Gennady ^a   Workman, Glenn O ^b   Veeraraghavan, Surya ^b   Shapira, Shye ^b   Stiles, Kevin ^c  

^a The Pennsylvania State University   (United States)

^b MOTOROLA INC   (United States)

^c AGERE SYSTEMS   (United States)

Author keywords

Compact model; Current partition; Direct tunneling; Gate tunneling current; MOSFET model; Surface potential

Indexed keywords

CURRENT DENSITY; ELECTRON TUNNELING; MATHEMATICAL MODELS; NUMERICAL ANALYSIS; SURFACE PROPERTIES; THICKNESS MEASUREMENT;

CURRENT PARTITION; GATE TUNNELING CURRENT; SURFACE POTENTIAL;

MOSFET DEVICES;

EID: 0742286722     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.820652     Document Type: Article

References (30)

1. H. C. Pao and C. T. Sah, "Effects of diffusion current on characteristics of metal-oxide(insulator)-semiconductor transistors," Solid State Electron., vol. 9, pp. 927-937, 1966.
2. J. R. Brews, "A charge-sheet model of the MOSFET," Solid State Electron., vol. 21, pp. 345-355, 1978.
3. C. Turchetti and G. Masetti, "A charge-sheet analysis of short-channel enhancement mode MOSFETs," IEEE J. Solid State Circuits, vol. SC-21, pp. 267-275, Apr. 1986.
4. K. Joardar, K. K. Gullapalli, C. C. McAndrew, M. E. Burhanm, and A. Wild, "An improved MOSFET model," IEEE Trans. Electron Devices, vol. 45, pp. 134-148, Jan. 1998.
5. Philips MOS Model 11, R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen. (2002, Dec.). [Online]. Available: http://www.semiconductors.philips.com/acrobat/other/philipsmodels/mos-models/mod el11/NLUR2002-802.pdf
6. C. C. McAndrew and J. J. Victory, "Accuracy of approximations in MOSFET charge models," IEEE Trans. Electron Devices, vol. 49, pp. 72-81, Jan. 2002.
7. T.-L. Chen and G. Gildenblat, "Overview of an advanced surface potential-based MOSFET model (SP)," in Proc. Int. Conf. Modeling Simulation of Microsystems (ICMSM'02), San Juan, Puerto Rico, Apr. 2002, pp. 657-661.
8. X. Gu, G. Gildenblat, G. Workman, S. Veeraraghavan, S. Shapira, and K. Stiles, "A surface potential-based extrinsic compact MOSFET model," in Proc. Int. Conf. Modeling and Simulation of Microsystems (ICMSM'03), San Francisco, CA, Feb. 2003, pp. 364-367.
9. K. F. Schuegraf, C. C. King, and C. Hu, "Ultra-thin silicon dioxide leakage current and scaling limit," in VLSI Sys. Tech. Dig., Seattle, WA., USA, June 1992, pp. 18-19.
10. L. F. Register, E. Rosenbaum, and K. Yang, "Analytic model for direct tunneling current in polycrystalline silicon-gate metal-oxide-semiconductor devices," Appl. Phys. Lett., vol. 74, pp. 457-459, 1999.
11. N. Yang, W. K. Henson, J. Hauser, and J. Wortman, "Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices," IEEE Trans. Electron Devices, vol. 46, pp. 1464-1471, July 1999.
12. C.-H. Choi, K.-H. Oh, J.-S. Goo, Z. Yu, and R. W. Dutton, "Direct tunneling current model for circuit simulation," in IEDM Tech. Dig., Washington, DC, Dec. 1999, pp. 735-738.
13. K. M. Cao et al., "BSIM4 gate leakage model including source-drain partition," in IEDM Tech. Dig., San Francisco, CA, Dec. 2000, pp. 815-818.
14. J. Cai and C. T. Sah, "gate-tunneling currents in ultrathin oxide metal-oxide-silicon transistors," J. Appl. Phys., vol. 89, pp. 2272-2285, 2001.
15. W.-C. Lee and C. Hu, "Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling," IEEE Trans. Electron Devices, vol. 48, pp. 1366-1373, June 2001.
16. R. van Langevelde et al., "Gate current: modeling, ΔL extraction and impact on RF performance," in IEDM Tech. Dig., Washington, DC, Dec. 2001, pp. 289-292.
17. W.-K. Shih et al., "A general partition scheme for gate leakage current suitable for MOSFET compact models," in IEDM Tech. Dig., Washington DC., Dec. 2001, pp. 293-296.
18. X. Gu, G. Gildenblat, G. Workman, S. Veeraraghavan, S. Shapira, and K. Stiles, "A surface potential-based compact model of nmosfet gate current," in Proc. Int. Conf. Modeling and Simulation of Microsystems (ICMSM'03), San Francisco, USA, Feb. 2003, pp. 318-321.
19. F. Rana, S. Tiwari, and D. Buchanan, "Self-consistent modeling of accumulation layers and tunneling currents through very thin oxides," Appl. Phys. Lett., vol. 69, pp. 1104-1106, 1996.
20. S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFETs," IEEE Electron Device Lett., vol. 18, pp. 209-211, May 1997.
21. W.-K. Shih et al., "Modeling gate leakage current in nmos structures due to tunneling through an ultra-thin oxide," Solid State Electron., vol. 42, pp. 997-1006, June 1998.
22. R. Tsu and L. Esaki, "Tunneling in a finite superlattice," Appl. Phys. Lett., vol. 22, pp. 562-564, 1973.
23. T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," in Tech. Dig. VLSI Sym., 2000, pp. 174-175.
24. T.-L. Chen and G. Gildenblat, "Analytical approximation for the MOSFET surface potential," Solid State Electron., vol. 45, no. 2, pp. 335-339, Feb. 2001.
25. Y. Shi, T. P. Ma, S. Prasad, and S. Dhanda, "Polarity dependent gate-tunneling currents in dual-gate CMOSFETs," IEEE Trans. Electron Devices, vol. 45, pp. 2355-2360, Nov. 1998.
26. T.-L. Chen and G. Gildenblat, "Symmetric bulk charge linearization in charge-sheet MOSFET model," Electron. Lett., vol. 37, no. 12, pp. 791-793, June 2001.
27. G. Gildenblat, T.-L. Chen, X. Gu, H. Wang, and X. Cai, "SP: an advanced surface potential-based compact MOSFET model," in Proc. Custom Integrated Circuit Conf. (Invited paper), Sept. 2003, pp. 233-240, to be published.
28. G. Gildenblat, T.-L. Chen, and P. Bendix, "Closed-form approximation for the perturbation of MOSFET surface potential by quantum-mechanical effects," Electron. Lett., vol. 36, no. 12, pp. 1072-1073, June 2000.
29. ____, "Analytical approximation for perturbation of MOSFET surface potential by polysilicon depletion layer," Electron. Lett., vol. 35, no. 22, pp. 1974-1976, Oct. 1999.
30. M. J. van Dort, P. H. Woerlee, and A. J. Walker, "A simple model for quantization effects in heavily-doped silicon MOSFETs at inversion conditions," Solid State Electron., vol. 37, no. 3, pp. 411-414, Mar. 1994.