A compact model for valence-band electron tunneling current in partially depleted SOI MOSFETs

IEEE Transactions on Electron Devices

Volumn 54, Issue 2, 2007, Pages 316-322

  Wu, Weimin ^a   Li, Xin ^a   Gildenblat, Gennady ^a   Workman, Glen O ^b   Veeraraghavan, Surya ^b   McAndrew, Colin C ^b   van Langevelde, Ronald ^c   Smit, Geert D J ^d   Scholten, Andries J ^d   Klaassen, Dirk B M ^d  

^a ARIZONA STATE UNIVERSITY   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

^d NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Hysteresis; Silicon on insulator (SOI); Surface potential; Symmetric linearization; Valence band electron (EVB) tunneling

Indexed keywords

COMPUTER SIMULATION; ELECTRON TUNNELING; GATES (TRANSISTOR); HYSTERESIS; LOGIC GATES; MATHEMATICAL MODELS; SILICON ON INSULATOR TECHNOLOGY; SURFACE POTENTIAL;

SYMMETRIC LINEARIZATION; VALENCE-BAND ELECTRON (EVB);

MOSFET DEVICES;

EID: 33847624495     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.888750     Document Type: Article

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