Benchmarking the PSP compact model for MOS transistors

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2007, Pages 259-264

  Li, Xin ^a   Wu, Weimin ^a   Jha, Amit ^a   Gildenblat, Gennady ^a   Van Langevelde, Ronald ^b   Smit, Geert D J ^c   Scholten, Andries J ^c   Klaassen, Dirk B M ^c   McAndrew, Colin C ^d   Watts, Josef ^e   Olsen, Michael ^e   Coram, Geoffrey ^f   Chaudhrytt, Samir ^g   Victory, James ^g  

^a Arizona State University   (United States)

^b TPhilips Research Laboratories   (Netherlands)

^c NXP SEMICONDUCTORS   (Netherlands)

^d FREESCALE SEMICONDUCTOR INC   (United States)

^e IBM RESEARCH   (United States)

^f ANALOG DEVICES INC   (United States)

^g Jazz Semiconductor   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; TRANSISTORS;

ANALOG APPLICATIONS; DATA STEMMING; SURFACE-POTENTIAL-BASED INDUSTRY STANDARD;

MOSFET DEVICES;

EID: 34548826225     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMTS.2007.374495     Document Type: Conference Paper

References (16)

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