Developing mesochronous synchronizers to enable 3D NoCs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 1414-1419

  Loi, Igor ^a   Angiolini, Federico ^a   Benini, Luca ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; INDUSTRIAL ENGINEERING; NONMETALS; SILICON; TESTING; TIMING CIRCUITS;

CIRCUIT DESIGNS; CLOCK SKEWS; CLOCK TREES; DEEP SUB MICRON TECHNOLOGIES; GAINING MOMENTUM; IMPLEMENTATION COSTS; MESOCHRONOUS; MESOCHRONOUS COMMUNICATION; NETWORK-ON-CHIP; PLACEMENT AND ROUTING; SILICON LAYERS; TIMING PROPERTIES;

BIOLOGICAL MATERIALS;

EID: 49749109850     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484872     Document Type: Conference Paper

References (35)

1. F. Angiolini, P. Meloni, S. Carta, L. Raffo, and L. Benini. A layout-aware analysis of networks-on-chip and traditional interconnects for MPSoCs. IEEE Transactions on Computer-Aided Design, 26(3):421-434, March 2007.
2. F. Angiolini, P. Meloni, S. Carta, L. Raffo, and L. Benini. A layout-aware analysis of networks-on-chip and traditional interconnects for mpsocs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(3):421-434, March 2007.
3. J. Bainbridge and S. Furber. Chain: a delay-insensitive chip area interconnect. IEEE Micro, 22(5):16-23, Sep/Oct 2002.
4. E. Beigne, F. Clermidy, P. Vivetand A. Clouard, and M. Renaudin. An asynchronous noc architecture providing low latency service and its multi-level design framework. In 11th IEEE International Symposium on Asynchronous Circuits and Systems, pages 54-63, 2005.
5. Luca Benini and Giovanni De Micheli. Networks on chip: a new SoC paradigm. IEEE Computer, 35(1):70-78, January 2002.
6. Tobias Bjerregaard and Jens Sparsø. Scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip. In Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pages 34-43, 2005.
7. William J. Dally and Brian Towles. Route packets, not wires: On-chip interconnection networks. In Proceedings of the 38th Design Automation Conference, pages 684-689, June 2001.
8. Brett Feero and Partha Pratim Pande. Performance evaluation for three-dimensional networks-on-chip. In Proceedings of the IEEE Annual Symposium on VLSI (ISVLSI), pages 305-310. IEEE Computer Society, 2007.
9. S. Fujita, K. Nomura, K. Abe, and T.H. Lee. 3d on-chip networking technology based on post-silicon devices for future networks-on-chip. In Nano-Networks and Workshops, pages 1-5, September 2006.
10. Maged Ghoneima, Yehea Ismail, Muhammad Khellah, and Vivek De. Variation-tolerant and low-power source-synchronous multicycle on-chip interconnection scheme. VLSI Design, 2007, 2007.
11. Eckhard Grass, Frank Winkler, Milos Krstic, Alexandra Julius, Christian Stahl, and Maxim Piz. Enhanced gals techniques for datapath applications. In PATMOS, pages 581-590, 2005.
12. Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, N. Vijaykrishnan, Mazin S. Yousif, and Chita R. Das. A novel dimensionally-decomposed router for on-chip communication in 3d architectures. In Proceedings of the 34th International Symposium on Computer Architecture (ISCA), 2007.
13. M. Krstic, E. Grass, C. Stahl, and M. Piz. System integration by request-driven gals design. IEE Proceedings on Computers and Digital Techniques, 153(5):362-372, September 2006.
14. D. Lattard and et al. A telecom baseband circuit-based on an asynchronous network-on-chip. In Proc. of the International Solid State Circuits Conference, ISSCC2007, pages 258-259, 2007.
15. Kangmin Lee, Se-Joong Lee, Sung-Eun Kim, Hye-Mi Choi, Donghyun Kim, Sunyoung Kim, Min-Wuk Lee, and Hoi-Jun Yoo. A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform. In Digest of Technical Papers of the 2004 IEEE International Solid-State Circuits Conference (ISSC), pages 152-518. IEEE Computer Society, 2004.
16. Kangmin Lee, Se-Joong Lee, and Hoi-Jun Yoo. Low-power network-on-chip for high-performance soc design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(2):148-160, February 2006.
17. Se-Joong Lee. Cost-optimization and chip implementation of on-chip network. Technical report, KAIST, 2005.
18. A. Lines. Asynchronous interconnect for synchronous soc design. IEEE Micro, 24(1):32-41, Jan-Feb 2004.
19. Igor Loi, Federico Angiolini, and Luca Benini. Supporting vertical links for 3d networks-on-chip: Toward an automated design and analysis flow. In Proceedings of the Nano-Net Conference 2007, 2007.
20. D. Mangano, R. Locatelli, A. Scandurra, C. Pistritto, M. Coppola, L. Fanucci, F. Vitullo, and D. Zandri. Skew insensitive physical links for network on chip. In 1st International Conference on Nano-Networks (NanoNet), pages 1-5, 2006.
21. Christopher A. Mineo. Clock tree insertion and verification for 3D integrated circuits. Technical report, North Carolina State University at Raleigh, 2005.
22. Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg Link, N. Vijaykrishnan, and Yehia Massoud. Thermally robust clocking schemes for 3D integrated circuits. In Proceedings of the 2007 Design, Automation and Test in Europe conference (DATE), pages 1206-1211, New York, NY, USA, 2007. ACM Press.
23. Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, and Giovanni De Micheli. Mapping and configuration methods for multi-use-case networks on chips. In Proceedings of the 2006 conference on Asia South Pacific design automation (ASP-DAC), pages 146-151, New York, NY, USA, 2006. ACM Press.
24. Srinivasan Murali and et al. Designing message-dependent deadlock free networks on chips for application-specific systems on chips. In VLSI-SoC, pages 158-163, 2006.
25. E. Nigussie, J. Plosila, and J. Isoaho. Delay-insensitive on-chip communication link using low-swing simultaneous bidirectional signaling. In Proceedings of the 2006 Emerging VLSI Technologies and Architectures (ISVLSI06), page 217, 2006.
26. Robert S. Patti. Three-dimensional integrated circuits and the future of system-on-chip designs. Proceedings of the IEEE, 94(6), June 2006.
27. Vasilis F. Pavlidis and Eby G. Friedman. 3-D topologies for networks-on-chip. In Proceedings of the IEEE SoC Conference (SOCC), pages 285-288. IEEE Computer Society, 2006.
28. L. A. Plana, W. J. Bainbridge, and S. B. Furber. The design and test of a smartcard chip using a CHAIN self-timed network-on-chip. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, page 274, 2004.
29. Dobkin Rostislav, Victoria Vishnyakov, Eyal Friedman, and Ran Ginosar. An asynchronous router for multiple service levels networks on chip. In Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, pages 44-53, 2005.
30. K. Srinivasan and K.S. Chatha. A methodology for layout aware design and optimization of custom network-on-chip architectures. In Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED). IEEE Computer Society, 2006.
31. S.Spiesshoefer and et al. Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development. In Electronic Components and Technology Conference, 2004.
32. Mikkel B. Stensgaard, Tobias Bjerregaard, Jens Sparso, and Johnny Halkjaer Pedersen. A simple clockless network-on-chip for a commercial audio DSP chip. In Proceedings of the 9th EUROMICRO Conference on Digital System Design, pages 641-648, 2006.
33. A. W. Topol, Jr. D. C. La Tulipe, L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong. Three-dimensional integrated circuits. IBM Journal of Research and Development, 50(4/5):491-506, July/September 2006.
34. Pascal T. Wolkotte, Philip K.F. Holzenspies, and Gerard J.M. Smit. Fast, accurate and detailed noc simulations. In Proceedings of the First International Symposium on Networks-on-Chip (NOCS). IEEE Computer Society, 2007.
35. Cesar Albenes Zeferino and Altamiro Amadeu Susin. SoCIN: A parametric and scalable network-on-chip. In Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI03), pages 34-43, 2003.