3D on-chip networking technology based on post-silicon devices for future networks-on-chip

2006 1st International Conference on Nano-Networks and Workshops, Nano-Net

Volumn , Issue , 2006, Pages

  Fujita, Shinobu ^a,b   Nomura, Kumiko ^a   Abe, Keiko ^a   Lee, Thomas H ^c  

^a TOSHIBA CORPORATION   (Japan)

^b Toshiba America Research Inc   (United States)

^c Stanford University   (United States)

Author keywords

3D circuit; Carbon nanotube; Interconnect delay; Nano mechanical electrical system; Nanowire; NEMS; Post silicon

Indexed keywords

CARBON NANOTUBES; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WIRE; FIELD EFFECT TRANSISTORS; MESFET DEVICES; NONMETALS; SILICON; THREE DIMENSIONAL;

3-D ARCHITECTURE; 3D CIRCUIT; CARBON NANOTUBE; FUTURE NETWORKS; HIGH-BANDWIDTH; INTERCONNECT DELAY; INTERNATIONAL CONFERENCES; LOW-LATENCY; NANO WIRES; NANO-MECHANICAL ELECTRICAL SYSTEM; NANO-NET; NANO-NETWORKS; NANOWIRE; NEMS; NETWORKING TECHNOLOGIES; ON CHIPS; POST-SILICON; SILICON DEVICES; THREE-DIMENSIONAL ARCHITECTURES;

TELECOMMUNICATION NETWORKS;

EID: 50149115653     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANONET.2006.346233     Document Type: Conference Paper

References (8)

1. Fujita, Shinobu., K. Nomura, K. Abe and T. H. Lee. "Novel architecture based on floating gate CNT-NEMS switches and its application to 3D on-chip bus beyond CMOS architecture." Proceedings of IEEE Nanotechnology Conference, Cincinnati, 2006 July.
2. K. Banerjee et al. "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and System-on-Chip Integration," Proceedings of the IEEE, vol.89, No.5, May 2001.
3. S. Kaeriyama et al., "A Nonvolatile Programmable Solid-Electrolyte Nanometer Switch," IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 168-176, Jan. 2005.
4. J.W. Ward et al., The 5th Annual Non-volatile Memory Technology Symposium, pp. 34-38, November 2004.
5. Lee S W et al., no. 10, pp. 2027-2030, 2004 Nanolett.
6. For example: Pham D. et al, "The Design and Implementation of a First-Generation CELL Processor," 2005 IEEE International Solid-State Circuits Conference (ISSCC2005) Digest of Technical Papers, pp. 184-185, Feb. 2005.
7. Jing Guo, Sayeed Hasan, Ali Javey, Gijs Bosman, and Mark Lundstrom "Assessment of High-Frequency Performance Potential for Carbon Nanotube Transistors." Unpublished. http://dynamo.ecn.purdue.edu/~lundstro/ Mark%20Lundstrom%20Publications.htm
8. B. Paul, M. Okajima, S. Fujita and T.H. Lee, "Modeling and Analysis of Circuit Performance of Ballistic CNFET," Proceedings of Design Automation Conference 2006, (SanFrancisco, USA); in press.