Supporting Vertical Links for 3D Networks-on-Chip: Toward an Automated Design and Analysis Flow

Nano-Net 2007 - Proceedings of the 2nd International Conference on Nano-Networks

Volumn , Issue , 2007, Pages

  Loi, Igor ^a   Angiolini, Federico ^a   Benini, Luca ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

3D Integrated Circuits; NoCs; Vertical Integration; Wafer Bonding

Indexed keywords

AUTOMATION; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; NETWORK ARCHITECTURE; NETWORK-ON-CHIP; SILICON WAFERS; TIMING CIRCUITS; WAFER BONDING;

3D NETWORKS; AUTOMATED ANALYSIS; AUTOMATED DESIGN; BANDWIDTH BOTTLENECKS; DESIGN AND ANALYSIS; DESIGN FLOWS; MANUFACTURING TECHNOLOGIES; NETWORKS ON CHIPS; VERTICAL INTEGRATION; VERTICAL LINKS;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84867757431     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.4108/ICST.NANONET2007.2033     Document Type: Conference Paper

References (33)

1. W. J. Dally and B. Towles, “Route packets, not wires: On-chip interconnection networks,” in Proceedings of the 38th Design Automation Conference, June 2001, pp. 684–689.
2. L. Benini and G. De Micheli, “Networks on chips: A new SoC paradigm,” IEEE Computer, vol. 35, no. 1, pp. 70 – 78, January 2002.
3. B. Rajendran, R. S. Shenoy, D. J. Witte, N. S. Chokshi, R. L. DeLeon, and G. S. Tompa, “Cmos transistor processing compatible with monolithic 3-d integration,” in Proc. VLSI Interconnection (VMIC), 2005, pp. 76–82.
4. Ziptronix, Ziptronix target vertical scalability, 2005.
5. S. Christiansen, R. Singh, and U. Gosele, “Wafer direct bonding: From advanced substrate engineering to future applications in micro/nanoelectronics,” in Proceedings of the IEEE, December 2006, pp. 2060–2106.
6. K. Lee, “Wafer-stacked package technology for high-performance system,” in RTI Int. technology Venture Forum, 2005.
7. S.Spiesshoefer and et al, “Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development,” in Electronic Components and Technology Conference, 2004.
8. R. S. Patti, “Three-dimensional integrated circuits and the future of system-on-chip designs,” Proceedings of the IEEE, vol. 94, no. 6, June 2006.
9. A. W. Topol, J. D. C. La Tulipe, L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, “Three-dimensional integrated circuits,” IBM Journal of Research and Development, vol. 50, no. 4/5, pp. 491–506, July/September 2006.
10. F. Karim, A. Nguyen, S. Dey, and R. Rao, “On-chip communication architecture for OC-768 network processors,” in Proceedings of the Design Automation Conference (DAC), 2001, pp. 678 – 683.
11. A. Pullini, F. Angiolini, D. Bertozzi, and L. Benini, “Fault tolerance overhead in network-on-chip flow control schemes,” in Proceedings of the 18th Annual Symposium on Integrated Circuits and System Design (SBCCI), 2005, pp. 224–229.
12. W. Hang-Sheng, Z. Xinping, P. Li-Shiuan, and S. Malik, “Orion: a power-performance simulator for interconnection networks,” in Proceedings of 35th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE/ACM, November 2002, pp. 294–305.
13. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, “QNoC: QoS architecture and design process for network on chip,” in Journal of Systems Architecture. Elsevier, 2004.
14. D. Wiklund and D. Liu, “SoCBUS: Switched network on chip for hard real time embedded systems,” in Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS03). IEEE, 2003.
15. T. Bjerregaard and J. Sparsø, “Scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip,” in Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2005, pp. 34–43.
16. A. Sheibanyrad, I. M. Panades, and A. Greiner, “Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture,” in Design, Automation & Test in Europe Conference & Exhibition, April 2007, pp. 1–6.
17. S. Furber and J. Bainbridge, “Future trends in soc interconnect,” in Proceedings of the International Symposium on System-on-Chip (SoC). IEEE Computer Society, 2005.
18. S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. D. Micheli, “Mapping and configuration methods for multi-use-case networks on chips,” in Proceedings of the 2006 conference on Asia South Pacific design automation (ASP-DAC). New York, NY, USA: ACM Press, 2006, pp. 146–151.
19. K. Srinivasan and K. Chatha, “A methodology for layout aware design and optimization of custom network-on-chip architectures,” in Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED). IEEE Computer Society, 2006.
20. A. Radulescu, J. Dielissen, K. Goossens, E. Rijpkema, and P. Wielage, “An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration,” in Proceedings of the 2004 Design, Automation and Test in Europe Conference (DATE). IEEE, 2004.
21. A. Andriahantenaina and A. Greiner, “Micro-network for SoC: Implementation of a 32-port SPIN network,” in The Proceedings of Design, Automation and Test in Europe Conference and Exhibition. IEEE, 2003, pp. 1128– 1129.
22. K. Lee, S.-J. Lee, S.-E. Kim, H.-M. Choi, D. Kim, S. Kim, M.-W. Lee, and H.-J. Yoo, “A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform,” in Digest of Technical Papers of the 2004 IEEE International Solid-State Circuits Conference (ISSC). IEEE Computer Society, 2004, pp. 152–518.
23. C. A. Zeferino and A. A. Susin, “SoCIN: A parametric and scalable network-on-chip,” in Proceedings of the 16th Symposium on Integrated Circuits and Systems Design (SBCCI03), 2003, pp. 34–43.
24. P. T. Wolkotte, P. K. Holzenspies, and G. J. Smit, “Fast, accurate and detailed noc simulations,” in Proceedings of the First International Symposium on Networks-on-Chip (NOCS). IEEE Computer Society, 2007.
25. F. Angiolini, P. Meloni, D. Bertozzi, L. Benini, S. Carta, and L. Raffo, “Networks on chips: A synthesis perspective,” in Proceedings of the 2005 ParCo Conference, 2005.
26. F. Angiolini, P. Meloni, S. Carta, L. Raffo, and L. Benini, “A layout-aware analysis of networks-on-chip and traditional interconnects for mpsocs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 3, pp. 421–434, March 2007.
27. V. F. Pavlidis and E. G. Friedman, “3-D topologies for networks-on-chip,” in Proceedings of the IEEE SoC Conference (SOCC). IEEE Computer Society, 2006, pp. 285–288.
28. B. Feero and P. P. Pande, “Performance evaluation for three-dimensional networks-on-chip,” in Proceedings of the IEEE Annual Symposium on VLSI (ISVLSI). IEEE Computer Society, 2007, pp. 305–310.
29. J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, M. S. Yousif, and C. R. Das, “A novel dimensionally-decomposed router for on-chip communication in 3d architectures,” in Proceedings of the 34th International Symposium on Computer Architecture (ISCA), 2007.
30. S. Fujita, K. Nomura, K. Abe, and T. Lee, “3d on-chip networking technology based on post-silicon devices for future networks-on-chip,” in Nano-Networks and Workshops, September 2006, pp. 1–5.
31. A. Corp., “Q3d extractor,” 2007, http://www.ansoft.com/products/si/q3dextractor/.
32. K. N. Chen, A. Fan, and C. S. T. ans R. Reif, “Contact resistance measurament of bonded copper interconnects for three-dimensional integration technology,” IEEE ELECTRON DEVICE LETTERS, vol. 25, no. 1, January 2005.
33. S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, and G. D. Micheli, “Designing application-specific networks on chips with floorplan information,” in Proceedings of the 2006 International Conference on Computer-Aided Design (ICCAD). New York, NY, USA: ACM Press, 2006, pp. 355–362.