A methodology for layout aware design and optimization of custom network-on-chip architectures

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 352-357

  Srinivasan, Krishnan ^a   Chatha, Karam S ^a  

^a Arizona State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION ENERGY; DESIGN AND OPTIMIZATION; INTEGER LINEAR PROGRAMMING; INTERCONNECTION ARCHITECTURE; NANOSCALE TECHNOLOGIES; NETWORK-ON-CHIP ARCHITECTURES; SYSTEM ON CHIP DESIGN; TOTAL ENERGY CONSUMPTION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; ENERGY UTILIZATION; HEURISTIC METHODS; INTEGER PROGRAMMING; MESH NETWORKING; NANOTECHNOLOGY; NETWORK ARCHITECTURE; OPTIMIZATION; SERVERS; TOPOLOGY; VLSI CIRCUITS;

BENCHMARKING;

EID: 49749095189     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.13     Document Type: Conference Paper

References (18)

1. W. J. Dally et al. "Route Packet, Not Wires: On-Chip Interconnection Networks". In Proceedings of DAC, June 2002.
2. L. Benini et al. "Networks on Chips: A New SoC Paradigm". IEEE Computer, pages 70-78, January 2002.
3. K. Srinivasan, et al. "A Technique for Design of Application Specific Network-on-Chip Architectures ". In Proceedings of DATE, Munich, Germany, March 2006.
4. K. Srinivasan et al. "An Automated Technique for Topology and Route Generation for Application Specific On-Chip Interconnection Networks". In Proceedings of ICCAD, San Jose, USA, October 2005.
5. S. Murali et al. "Mapping and Physical Planning of Networks-on-Chip Architectures with Quality-of-Service Guarantees ". In Proceedings of ASPDAC, 2005.
6. N. Banerjee et al. "A Power and Performance Model for Network-on-Chip Architectures ". In Proceedings of DATE, Paris, France, February 2004.
7. G. Ascia et al. "Multi-objective Mapping for Mesh-based NoC Architectures". In Proceedings of ISSS-CODES, 2004.
8. S. Murali, and G. De Micheli. "Bandwidth-Constrained Mapping of Cores onto NoC Architectures". In DATE, 2004.
9. J. Hu et al. "Energy-Aware Mapping for Tile-based NoC Architectures Under Performance Constraints". In ASP-DAC, 2003.
10. K. Srinivasan et al. "Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures ". In Proceedings of ICCD, San Jose, USA, October 2004.
11. K. Srinivasan et al. "ISIS: A Genetic Algorithm based Technique for Synthesis of On-Chip Interconnection Networks ". In Proceedings of VLSI Design, Calcutta, India, January 2005.
12. K. Srinivasan et al. "SAGA: Synthesis Technique for Guaranteed Throughput NoC Architectures". In Proceedings of ASPDAC, Shanghai, China, January 2005.
13. Umit Ogras et al. "Energy and Performance Driven NoC Communication Architecture Synthesis Using A Decomposition Approach". In DATE, 2005.
14. A. Pinto et al. "Efficient Synthesis of Networks On Chip". In ICCD, 2003.
15. J.G Kim et al. "A Linear Programming Based Algorithm for Floorplanning in VLSI Design". IEEE Transactions on CAD, 22(5), 2003.
16. W.J. Dally et al. "Deadlock-free message routing in multiprocessor interconnection networks". "IEEE Transactions on Computers", C-36(5):547-553, 1987.
17. D'andrade R. "U-Statistic Hierarchical Clustering". Psychometrica, 4(58-67), 1978.
18. "www.dashoptimization.com" 2004.