The design and test of a smartcard Chip using a CHAIN self-timed Network-on-Chip

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn , Issue , 2004, Pages 274-279

  Bainbridge, W J ^a   Plana, L A ^a   Furber, S B ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DEBUGGING; NETWORK ON CHIP (NOC); SELF-TIMED PROCESSORS; TIMING ANALYSIS;

COMPUTER ARCHITECTURE; COMPUTER NETWORKS; INTERCONNECTION NETWORKS; LEGACY SYSTEMS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS;

SMART CARDS;

EID: 3042515271     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269249     Document Type: Conference Paper

References (11)

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