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Volumn , Issue , 2005, Pages 44-53

An asynchronous router for multiple service levels Networks on Chip

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; MICROPROCESSOR CHIPS; QUALITY OF SERVICE;

EID: 28444449827     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2005.11     Document Type: Conference Paper
Times cited : (71)

References (28)
  • 2
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: On-chip interconnection networks
    • June
    • W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proc. DAC, June 2001.
    • (2001) Proc. DAC
    • Dally, W.J.1    Towles, B.2
  • 6
    • 0036761283 scopus 로고    scopus 로고
    • Chain: A delay-insensitive chip area interconnect
    • Sep./Oct.
    • J.Bainbridge and S.Furber, "Chain: a Delay-Insensitive Chip Area Interconnect," IEEE Micro, vol. 22, no.5, pp. 16-23, Sep./Oct. 2002.
    • (2002) IEEE Micro , vol.22 , Issue.5 , pp. 16-23
    • Bainbridge, J.1    Furber, S.2
  • 7
    • 3042515271 scopus 로고    scopus 로고
    • The design and test of a smartcard chip using a CHAIN self-timed Network-on-Chip
    • Feb.
    • W.J. Bainbridge, L.A. Plana and S.B. Furber, "The Design and Test of a Smartcard Chip Using a CHAIN Self-timed Network-on-Chip," Proc. DATE, Feb. 2004.
    • (2004) Proc. DATE
    • Bainbridge, W.J.1    Plana, L.A.2    Furber, S.B.3
  • 8
    • 14844314436 scopus 로고    scopus 로고
    • An asynchronous on-chip network router with Quality-of-Service (QoS) support
    • Santa Clara, CA, Sept.
    • T.Felicijan, S.B.Furber, "An Asynchronous On-Chip Network Router with Quality-of-Service (QoS) Support," Proc. of IEEE International SOC Conference, Santa Clara, CA, Sept. 2004, pp. 274-277.
    • (2004) Proc. of IEEE International SOC Conference , pp. 274-277
    • Felicijan, T.1    Furber, S.B.2
  • 9
    • 3042565282 scopus 로고    scopus 로고
    • A power and performance model for Network-on-Chip architectures
    • N. Banerjee, P. Vellanki and K.S. Chatha, "A Power and Performance Model for Network-on-Chip Architectures," DATE 2004.
    • DATE 2004
    • Banerjee, N.1    Vellanki, P.2    Chatha, K.S.3
  • 10
    • 2942641861 scopus 로고    scopus 로고
    • Quality-of-Service and error control techniques for Network-on-Chip architectures
    • Boston, USA
    • P. Vellanki, N. Banerjee and K.S. Chatha, "Quality-of-Service and Error Control Techniques for Network-on-Chip Architectures," Proc. GLSVLSI'04, Boston, USA, pp. 45-50, 2004.
    • (2004) Proc. GLSVLSI'04 , pp. 45-50
    • Vellanki, P.1    Banerjee, N.2    Chatha, K.S.3
  • 14
    • 84862144932 scopus 로고    scopus 로고
    • Power driven design of router microarchitectures in on-chip networks
    • H. Wang, L.S. Peh and S. Malik, "Power Driven Design of Router Microarchitectures in On-Chip Networks," Proc. MICRO-36, 2003.
    • (2003) Proc. MICRO-36
    • Wang, H.1    Peh, L.S.2    Malik, S.3
  • 15
    • 0345358582 scopus 로고    scopus 로고
    • Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip
    • Sept.
    • E. Rijpkema, K. Goossens et al., "Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip," IEE Proc.-Comp. Digit. Tech., 150(5), 294-302, Sept. 2003.
    • (2003) IEE Proc.-comp. Digit. Tech. , vol.150 , Issue.5 , pp. 294-302
    • Rijpkema, E.1    Goossens, K.2
  • 18
    • 77957968874 scopus 로고    scopus 로고
    • Clock synchronization through handshake signalling
    • March
    • J. Kessels, A. Peeters, P. Wielage and S.-J. Kim, "Clock Synchronization through Handshake Signalling," Proc. ASYNC, pp. 59-68, March 2002.
    • (2002) Proc. ASYNC , pp. 59-68
    • Kessels, J.1    Peeters, A.2    Wielage, P.3    Kim, S.-J.4
  • 19
    • 77957969505 scopus 로고    scopus 로고
    • Self-timed ring for globally-asynchronous locally-synchronous systems
    • April
    • T. Villiger, H. Kaeslin, F.K. Gürkaynak, S. Oetiker and W. Fichtner, "Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems," Proc. ASYNC, pp. 141-150, April 2003.
    • (2003) Proc. ASYNC , pp. 141-150
    • Villiger, T.1    Kaeslin, H.2    Gürkaynak, F.K.3    Oetiker, S.4    Fichtner, W.5
  • 20
    • 77957961901 scopus 로고    scopus 로고
    • Practical design of globally-asynchrounous locally-synchronous systems
    • April
    • J. Muttersbach, T. Villiger and W. Fichtner, "Practical Design of Globally-Asynchrounous Locally-Synchronous Systems," Proc. ASYNC, pp. 52-61, April 2000.
    • (2000) Proc. ASYNC , pp. 52-61
    • Muttersbach, J.1    Villiger, T.2    Fichtner, W.3
  • 27
    • 0032656236 scopus 로고    scopus 로고
    • Ordered arbiters
    • 27th May
    • A. Bystrov and A. Yakovlev, "Ordered arbiters," Electronics Letters, 35(11), pp. 877-879, 27th May 1999.
    • (1999) Electronics Letters , vol.35 , Issue.11 , pp. 877-879
    • Bystrov, A.1    Yakovlev, A.2
  • 28
    • 84945270100 scopus 로고    scopus 로고
    • An asynchronous low latency arbiter for Quality of Service (QoS) applications
    • Cairo, Egypt, Dec.
    • T. Felicijan, J. Bainbridge and S. Furber, "An Asynchronous Low Latency Arbiter for Quality of Service (QoS) Applications," Proc. Int. Conf. Microelectronics (IMC), Cairo, Egypt, pp. 123-126, Dec. 2003.
    • (2003) Proc. Int. Conf. Microelectronics (IMC) , pp. 123-126
    • Felicijan, T.1    Bainbridge, J.2    Furber, S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.