Chain: A delay-insensitive chip area interconnect

IEEE Micro

Volumn 22, Issue 5, 2002, Pages 16-23

  Bainbridge, John ^a   Furber, Steve ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0036761283     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2002.1044296     Document Type: Review

References (11)

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3. H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Boston, 1990.
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7. W.J. Bainbridge and S.B. Furber, "Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding," Proc. 7th IEEE Int'l Symp. Asynchronous Circuits and Systems (Async), IEEE CS Press, Los Alamitos, Calif., 2001, pp. 118-126.
8. Open Core Protocol Specification, OCP International Partnership (OCP-IP), Portland, Ore.; http://www.ocpip.org (current Aug. 2002).
9. Advanced Microcontroller Bus Architecture (AMBA) Specification Rev. 2.0, ARM Ltd., document no. IHI-0011A, May 1999; http://www.arm.com (current Aug. 2002).
10. J. Bainbridge, Asynchronous System-on-Chip Interconnect, Springer, Heidelberg, Germany, 2002.
11. L.A. Plana et al., "SPA-A Synthesizable Amulet Core for Smartcard Applications," Proc. 8th IEEE Int'l Symp. Asynchronous Circuits and Systems (Async), IEEE CS Press, Los Alamitos, Calif., 2002, pp. 201-210.