Performance evaluation for three-dimensional networks-on-chip

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Volumn , Issue , 2007, Pages 305-310

  Feero, Brett ^a   Pande, Partha Pratim ^a  

^a Washington State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED CORES; PACKAGING DENSITY; PERFORMANCE EVALUATION; THREE-DIMENSIONAL NETWORKS-ON-CHIP;

COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; ENERGY DISSIPATION; MICROPROCESSOR CHIPS; SILICON COMPOUNDS; THREE DIMENSIONAL;

INTEGRATED CIRCUITS;

EID: 36349019639     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2007.79     Document Type: Conference Paper

References (9)

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