3-D topologies for Networks-on-Chip

2006 IEEE International Systems-on-Chip Conference, SOC

Volumn , Issue , 2006, Pages 285-288

  Pavlidis, Vasilis F ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); ELECTRIC NETWORK TOPOLOGY; THREE DIMENSIONAL COMPUTER GRAPHICS;

NETWORKS-ON-CHIP (NOC); ZERO-LOAD LATENCY;

MICROPROCESSOR CHIPS;

EID: 43749118934     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2006.283899     Document Type: Conference Paper

References (10)

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9. Metal User's Guide, OEA International Inc.
10. L. N. Bhuyan and D. P. Agrawal, "Generalized Hypercube and Hyperbus Structures for a Computer Network," IEEE Transactions on Computers, Vol. C-33, No. 4, pp. 323-333, April 1984.