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Volumn , Issue , 2007, Pages 323-332

Fast, accurate and detailed NoC simulations

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PARAMETER ESTIMATION; ROUTERS; TELECOMMUNICATION TRAFFIC;

EID: 36348941764     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2007.18     Document Type: Conference Paper
Times cited : (66)

References (19)
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  • 9
    • 0003886631 scopus 로고    scopus 로고
    • European Telecommunication Standard Institute (ETSI, ETSI TS 101 475 v1.2.2 (2001-02) edition, February
    • European Telecommunication Standard Institute (ETSI). Broadband Radio Access Networks (BRAN); HIPERLAN Type 2, ETSI TS 101 475 v1.2.2 (2001-02) edition, February 2001.
    • (2001) Broadband Radio Access Networks (BRAN); HIPERLAN Type 2
  • 10
    • 33646925675 scopus 로고    scopus 로고
    • A complete network-on-chip emulation framework
    • N. Genko et al. A complete network-on-chip emulation framework. In Proceedings of DATE'05, pages 246-251, 2005.
    • (2005) Proceedings of DATE'05 , pp. 246-251
    • Genko, N.1
  • 11
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    • A design flow for application-specific networks on chip with guaranteed performance to accelerate soc design and verification
    • Washington, DC, USA, IEEE Computer Society
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    • Goossens, K.1
  • 12
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  • 14
    • 1142299901 scopus 로고    scopus 로고
    • A modular simulation framework for architectural exploration of on-chip interconnection networks
    • New York, NY, USA, ACM Press
    • T. Kogel et al. A modular simulation framework for architectural exploration of on-chip interconnection networks. In Proceedings of CODES+ISSS'03, pages 7-12, New York, NY, USA, 2003. ACM Press.
    • (2003) Proceedings of CODES+ISSS'03 , pp. 7-12
    • Kogel, T.1
  • 15
    • 35248833754 scopus 로고    scopus 로고
    • T. Marescaux et al. Networks on Chip as Hardware Components of an OS for Reconfigurable Systems. In Field-Programmable Logic and Applications, 2778/2003 of Lecture Notes in Computer Science, pages 595-605. Springer Berlin / Heidelberg, 2003.
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  • 16
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    • Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip
    • sep
    • E. Rijpkema et al. Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip. IEE Proceedings: Computers and Digital Techniques, 150(5):294-302, sep 2003.
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  • 17
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    • Seoul, Korea, October, ACM Press
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.