Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ILP and streams

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn 31, Issue , 2004, Pages 2-13

  Taylor, Michael Bedford ^a   Lee, Walter ^a   Miller, Jason ^a   Wentzlaff, David ^a   Bratt, Ian ^a   Greenwald, Ben ^a   Hoffmann, Henry ^a   Johnson, Paul ^a   Kim, Jason ^a   Psota, James ^a   Saraf, Arvind ^a   Shnidman, Nathan ^a   Strumpen, Volker ^a   Frank, Matt ^a   Amarasinghe, Saman ^a   Agarwal, Anant ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTING APPLICATIONS; DATA TRANSPORT; PENTIUM III; RAW MICROPROCESSORS;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE; DATA TRANSFER; DELAY CIRCUITS; FEEDBACK; FIELD PROGRAMMABLE GATE ARRAYS; SOFTWARE PROTOTYPING; VLSI CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 4644353790     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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