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Volumn 2006, Issue , 2006, Pages 15-26

CMP design space exploration subject to physical constraints

Author keywords

[No Author keywords available]

Indexed keywords

PIPELINE DEPTH; POWER DENSITY; SUPERSCALAR WIDTH; THERMAL CONSTRAINTS;

EID: 33748857902     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2006.1598109     Document Type: Conference Paper
Times cited : (109)

References (26)
  • 4
    • 22944440036 scopus 로고    scopus 로고
    • High performance throughput computing
    • May/June
    • S. Chaudhry, P. Caprioli, S. Yip, and M. Tremblay. High performance throughput computing. IEEE Micro, 25(3):32-45, May/June 2005.
    • (2005) IEEE Micro , vol.25 , Issue.3 , pp. 32-45
    • Chaudhry, S.1    Caprioli, P.2    Yip, S.3    Tremblay, M.4
  • 9
    • 0036287089 scopus 로고    scopus 로고
    • The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
    • May
    • M. S. Hrishikesh et al. The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays. In Proc. of the 29th Int'l Symp. on Computer Architecture, pages 14-24, May 2002.
    • (2002) Proc. of the 29th Int'l Symp. on Computer Architecture , pp. 14-24
    • Hrishikesh, M.S.1
  • 12
    • 20344374162 scopus 로고    scopus 로고
    • Niagara: A 32-way multithreaded sparc processor
    • Mar./Apr.
    • P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded sparc processor. IEEE Micro, 25(2):21-29, Mar./Apr. 2005.
    • (2005) IEEE Micro , vol.25 , Issue.2 , pp. 21-29
    • Kongetira, P.1    Aingaran, K.2    Olukotun, K.3
  • 13
    • 0019056989 scopus 로고
    • Computer system design using a hierarchical approach to performance evaluation
    • Sep.
    • B. Kumar and E. S. Davidson. Computer system design using a hierarchical approach to performance evaluation. In Communications of the ACM, 23(9), Sep. 1980.
    • (1980) Communications of the ACM , vol.23 , Issue.9
    • Kumar, B.1    Davidson, E.S.2
  • 14
    • 27544456315 scopus 로고    scopus 로고
    • Interconnections in multicore architectures: Understanding mechanisms, overheads and scaling
    • June
    • R. Kumar, V. Zyuban, and D. M. Tullsen. Interconnections in multicore architectures: Understanding mechanisms, overheads and scaling. In The 32nd Int'l Symp. on Computer Architecture, June. 2005.
    • (2005) The 32nd Int'l Symp. on Computer Architecture
    • Kumar, R.1    Zyuban, V.2    Tullsen, D.M.3
  • 18
    • 33748861897 scopus 로고    scopus 로고
    • Performance, energy and thermal, considerations for SMT and CMP architectures: Extended discussion and results
    • Univ. of Virginia Dept. of Computer Science, Oct.
    • Y. Li, D. Brooks, Z. Hu, and K. Skadron. Performance, energy and thermal, considerations for SMT and CMP architectures: Extended discussion and results. Technical Report CS-2004-32, Univ. of Virginia Dept. of Computer Science, Oct. 2004.
    • (2004) Technical Report , vol.CS-2004-32
    • Li, Y.1    Brooks, D.2    Hu, Z.3    Skadron, K.4
  • 19
    • 0032683935 scopus 로고    scopus 로고
    • Environment forpowerpc microarchitecture exploration
    • May/Jun.
    • M. Moudgill, J. Wellman, and J. Moreno. Environment forpowerpc microarchitecture exploration. IEEE Micro, 19(3), May/Jun. 1999.
    • (1999) IEEE Micro , vol.19 , Issue.3
    • Moudgill, M.1    Wellman, J.2    Moreno, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.