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Volumn , Issue , 2006, Pages 625-632

Thermal trends in emerging Technologies

Author keywords

[No Author keywords available]

Indexed keywords

EMERGING TECHNOLOGIES; MULTI-LAYER DEVICES; PEAK TEMPERATURES; PLACEMENT OPTIMIZATION; POWER DISTRIBUTIONS; PROCESS VARIATION; SWITCHING ACTIVITIES; VERTICAL TEMPERATURE DIFFERENCES;

EID: 84864864951     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.136     Document Type: Conference Paper
Times cited : (61)

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    • WAttch: A framework for architectural-level power analysis and optimizations
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    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 7
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    • A new analytical thermal model for multilevel ulsi interconnects incorporating via effects
    • San Fransisco, CA, USA, June. IEEE
    • T.-Y. Chiang, K. Banerjee, and K. C. Saraswat. A New Analytical Thermal Model for Multilevel ULSI Interconnects Incorporating Via Effects. In IEEE International Interconnect Technology Conference (IITC), pages 92-94, San Fransisco, CA, USA, June 2001. IEEE.
    • (2001) IEEE International Interconnect Technology Conference (IITC) , pp. 92-94
    • Chiang, T.-Y.1    Banerjee, K.2    Saraswat, K.C.3
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    • Threshold voltage mismatch and intra-die leakage current in digital cmos circuits
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    • J. P. Gyvez and H. P. Tuinhout. Threshold Voltage Mismatch and Intra-Die Leakage Current in Digital CMOS Circuits. IEEE Transactions on Solid-State Circuits, 39(1):157-168, January 2004.
    • (2004) IEEE Transactions on Solid-State Circuits , vol.39 , Issue.1 , pp. 157-168
    • Gyvez, J.P.1    Tuinhout, H.P.2
  • 14
    • 1542269365 scopus 로고    scopus 로고
    • Statistical esimation of leakage current considering inter-and intra-die process variation
    • R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester. Statistical Esimation of Leakage Current Considering Inter-and Intra-Die Process Variation. In ISLPED, pages 84-89, 2003.
    • (2003) ISLPED , pp. 84-89
    • Rao, R.1    Srivastava, A.2    Blaauw, D.3    Sylvester, D.4
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    • Thermal characterization of bare-die stacked modules with cu through-vias
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.