-
1
-
-
33646900503
-
Device scaling limits of Si MOSFETs and their application dependencies
-
Mar
-
E. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong. Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE, 89(3): 259-288, Mar. 2001.
-
(2001)
Proc. IEEE
, vol.89
, Issue.3
, pp. 259-288
-
-
Frank, E.J.1
Dennard, R.H.2
Nowak, E.3
Solomon, P.M.4
Taur, Y.5
Wong, H.-S.P.6
-
2
-
-
16244422171
-
Interconnect-power dissipation in a microprocessor
-
Feb
-
N. Magen, A. Kolodny, U. Weiser, and N. Shamir. Interconnect-power dissipation in a microprocessor. In Proc. Wkshp. System-Level Interconnect Prediction, pages 7-13, Feb. 2004.
-
(2004)
Proc. Wkshp. System-Level Interconnect Prediction
, pp. 7-13
-
-
Magen, N.1
Kolodny, A.2
Weiser, U.3
Shamir, N.4
-
3
-
-
0037703176
-
The scaling challenge: Can correct-by-construction design help?
-
Apr
-
P. Saxena, N. Menezes, P. Cocchini, and D. A. Kirkpatrick. The scaling challenge: Can correct-by-construction design help? In Proc. IEEE Intl. Symp. Physical Design, pages 51-58, Apr. 2003.
-
(2003)
Proc. IEEE Intl. Symp. Physical Design
, pp. 51-58
-
-
Saxena, P.1
Menezes, N.2
Cocchini, P.3
Kirkpatrick, D.A.4
-
4
-
-
47649101121
-
-
2005 International Technology Roadmap for Semiconductors
-
2005 International Technology Roadmap for Semiconductors. http://www.itrs.net/Links/2005ITRS/Home2005.htm.
-
-
-
-
5
-
-
33751396182
-
FinFETs for nanoscale CMOS digital integrated circuits
-
Nov
-
T.-J. King. FinFETs for nanoscale CMOS digital integrated circuits. In Proc. Int. Conf. Computer-Aided Design, pages 207-210, Nov. 2005.
-
(2005)
Proc. Int. Conf. Computer-Aided Design
, pp. 207-210
-
-
King, T.-J.1
-
6
-
-
34249795033
-
Gate sizing: FinFETs vs 32nm bulk MOSFETs
-
July
-
B. Swahn and S. Hassoun. Gate sizing: FinFETs vs 32nm bulk MOSFETs. In Proc. Design Automation Conf., pages 528-531, July 2006.
-
(2006)
Proc. Design Automation Conf
, pp. 528-531
-
-
Swahn, B.1
Hassoun, S.2
-
8
-
-
27844480979
-
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages
-
Sept
-
A. U. Dirl, Y. S. Dhillon, A. Chatterjee, and A. D. Singh. Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. IEEE Trans. VLSI Systems, 13(9): 1103-1107, Sept. 2005.
-
(2005)
IEEE Trans. VLSI Systems
, vol.13
, Issue.9
, pp. 1103-1107
-
-
Dirl, A.U.1
Dhillon, Y.S.2
Chatterjee, A.3
Singh, A.D.4
-
9
-
-
0242695816
-
Power disspation issues in interconnect performance optimization for sub-180nm designs
-
June
-
K. Banerjee and A. Mehrotra. Power disspation issues in interconnect performance optimization for sub-180nm designs. In Proc. VLSI Symp. Technology & Circuits, pages 12-15, June 2002.
-
(2002)
Proc. VLSI Symp. Technology & Circuits
, pp. 12-15
-
-
Banerjee, K.1
Mehrotra, A.2
-
10
-
-
0025594311
-
Buffer placement in distributed RC-tree networks for minimal elmore delay
-
June
-
L. P. P. P. van Ginneken. Buffer placement in distributed RC-tree networks for minimal elmore delay. In Proc. Int. Symp. Circuits & Systems, pages 865-868, June 1990.
-
(1990)
Proc. Int. Symp. Circuits & Systems
, pp. 865-868
-
-
van Ginneken, L.P.P.P.1
-
11
-
-
0030110490
-
Optimal wire sizing and buffer insertion for low power and a generalized delay model
-
J. Lillils, C. K. Cheng, and T-T. Y. Lin. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE J. Solid-State Circuits, 31(3):437-447, 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, Issue.3
, pp. 437-447
-
-
Lillils, J.1
Cheng, C.K.2
Lin, T.-T.Y.3
-
12
-
-
0041633712
-
-
W. Shi and Z. Li. An O(nlogn) time algorithm for optimal buffer insertion. In Proc. Design Automation Conf., pages 580-585, June 2003.
-
W. Shi and Z. Li. An O(nlogn) time algorithm for optimal buffer insertion. In Proc. Design Automation Conf., pages 580-585, June 2003.
-
-
-
-
13
-
-
27944470532
-
dd buffered tree considering buffer stations and blockages
-
June
-
dd buffered tree considering buffer stations and blockages. In Proc. Design Automation Conf., pages 497-502, June 2005.
-
(2005)
Proc. Design Automation Conf
, pp. 497-502
-
-
Tam, K.H.1
He, L.2
-
14
-
-
34748845673
-
-
dd buffering based on interconnect prediction and sampling. In Proc. Wkshp. System-Level Interconnect Prediction, pages 95-102, Mar. 2007.
-
dd buffering based on interconnect prediction and sampling. In Proc. Wkshp. System-Level Interconnect Prediction, pages 95-102, Mar. 2007.
-
-
-
-
16
-
-
1842865629
-
Turning silicon on its edge
-
Jan.-Feb
-
E. J. Nowak, I. Aller, T. Ludwig, K. Kim, R. V. Joshi, C.-T. Chuang, K. Bernstein, and R. Puri. Turning silicon on its edge. IEEE Circuits and Devices Magazine, 20(1): 20-31, Jan.-Feb. 2004.
-
(2004)
IEEE Circuits and Devices Magazine
, vol.20
, Issue.1
, pp. 20-31
-
-
Nowak, E.J.1
Aller, I.2
Ludwig, T.3
Kim, K.4
Joshi, R.V.5
Chuang, C.-T.6
Bernstein, K.7
Puri, R.8
-
17
-
-
33744745861
-
Independent gate skewed logic in double-gate SOI technology
-
Oct
-
T. Cakici, H. Mahmoodi, S. Mukhopadhyay, and K. Roy. Independent gate skewed logic in double-gate SOI technology. In Proc. IEEE Int. SOI Conf., pages 83-84, Oct. 2005.
-
(2005)
Proc. IEEE Int. SOI Conf
, pp. 83-84
-
-
Cakici, T.1
Mahmoodi, H.2
Mukhopadhyay, S.3
Roy, K.4
-
18
-
-
47649089640
-
A high-performance, low leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology
-
Jan
-
R. V. Joshi, K. Kim, R. Q. Williams, E. J. Nowak, and C.-T. Chuang. A high-performance, low leakage, and stable SRAM row-based back-gate biasing scheme in FinFET technology. In Proc. Int. Conf. VLSI Design, pages 665-672, Jan. 2007.
-
(2007)
Proc. Int. Conf. VLSI Design
, pp. 665-672
-
-
Joshi, R.V.1
Kim, K.2
Williams, R.Q.3
Nowak, E.J.4
Chuang, C.-T.5
-
19
-
-
0031335844
-
Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs
-
Oct
-
L. Wei, Z. Chen, and K. Roy. Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs. In Proc. IEEE Int. SOI Conf., pages 82-83, Oct. 1997.
-
(1997)
Proc. IEEE Int. SOI Conf
, pp. 82-83
-
-
Wei, L.1
Chen, Z.2
Roy, K.3
-
20
-
-
29244446292
-
Low-power circuits using dynamic threshold voltage devices
-
Apr
-
P. Beckett. Low-power circuits using dynamic threshold voltage devices. In Proc. Great Lakes Symp. VLSI, pages 213-216, Apr. 2005.
-
(2005)
Proc. Great Lakes Symp. VLSI
, pp. 213-216
-
-
Beckett, P.1
-
21
-
-
34748840102
-
Optimizing FinFET technology for high-speed and low-power design
-
Mar
-
T. Sairam, W. Zhao, and Y. Cao. Optimizing FinFET technology for high-speed and low-power design. In Proc. Great Lakes Symp. VLSI, pages 73-77, Mar. 2007.
-
(2007)
Proc. Great Lakes Symp. VLSI
, pp. 73-77
-
-
Sairam, T.1
Zhao, W.2
Cao, Y.3
-
22
-
-
33846826993
-
Threshold voltage and bulk inversion effects in nonclassical CMOS devices with undoped ultra-thin bodies
-
Dec
-
V. P. Trivedi, J. G. Fossum, and W. Zhang. Threshold voltage and bulk inversion effects in nonclassical CMOS devices with undoped ultra-thin bodies. Solid-State Electronics, 1(1): 170-178, Dec. 2007.
-
(2007)
Solid-State Electronics
, vol.1
, Issue.1
, pp. 170-178
-
-
Trivedi, V.P.1
Fossum, J.G.2
Zhang, W.3
-
23
-
-
84886736952
-
New generation of predictive technology model for sub-45nm design exploration
-
May
-
W. Zhao and Y. Cao. New generation of predictive technology model for sub-45nm design exploration. In Proc. Int. Symp. Quality of Electronic Design, pages 585-590, May 2006. http://www.eas.asu.edu/~ptm.
-
(2006)
Proc. Int. Symp. Quality of Electronic Design
, pp. 585-590
-
-
Zhao, W.1
Cao, Y.2
-
24
-
-
34247502116
-
Predictive technology model for nano-CMOS design exploration
-
Apr
-
W. Zhao and Y. Cao. Predictive technology model for nano-CMOS design exploration. ACM J. Emerging Technologies in Computing Systems, 3(1):1-17, Apr. 2007.
-
(2007)
ACM J. Emerging Technologies in Computing Systems
, vol.3
, Issue.1
, pp. 1-17
-
-
Zhao, W.1
Cao, Y.2
-
25
-
-
33749341857
-
Dependability analysis of FinFET circuits
-
Mar
-
F. Wang, Y. Xie, K. Bernstein, and Y. Luo. Dependability analysis of FinFET circuits. In Proc. IEEE Computer Soc. Symp. Emerging VLSI Technologies and Architectures, pages 399-404, Mar. 2006.
-
(2006)
Proc. IEEE Computer Soc. Symp. Emerging VLSI Technologies and Architectures
, pp. 399-404
-
-
Wang, F.1
Xie, Y.2
Bernstein, K.3
Luo, Y.4
-
26
-
-
10644265317
-
Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs
-
Dec
-
D. Ha, H. Takeuchi, Y.-K. Choi, and T.-J. King. Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs. IEEE Trans. Electron Devices, 51 (12): 1989-1996, Dec. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.12
, pp. 1989-1996
-
-
Ha, D.1
Takeuchi, H.2
Choi, Y.-K.3
King, T.-J.4
-
27
-
-
0004008244
-
-
McGraw Hill, New York, NY, 3rd edition
-
D. A. Hodges, H. G. Jackson, and R. A. Saleh. Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology. McGraw Hill, New York, NY, 3rd edition, 2004.
-
(2004)
Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology
-
-
Hodges, D.A.1
Jackson, H.G.2
Saleh, R.A.3
-
28
-
-
2342646021
-
-
Addison Wesley, Reading, MA, 3rd edition
-
N. Weste and D. Harris. CMOS VLSI Design. Addison Wesley, Reading, MA, 3rd edition, 2000.
-
(2000)
CMOS VLSI Design
-
-
Weste, N.1
Harris, D.2
-
29
-
-
2942659739
-
A scalable communication-centric SoC interconnect architecture
-
C. Grecu, P. P. Pande, A. Ivanov, and R. Saleh. A scalable communication-centric SoC interconnect architecture. In Proc. Int. Symp. Quality of Electronic Design, pages 343-348, 2004.
-
(2004)
Proc. Int. Symp. Quality of Electronic Design
, pp. 343-348
-
-
Grecu, C.1
Pande, P.P.2
Ivanov, A.3
Saleh, R.4
-
30
-
-
37749001321
-
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits
-
Nov
-
J. H. Choi, A. Bansal, M. Meterelliyoz, J. Murthy, and K. Roy. Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. In Proc. Int. Conf. Computer-Aided Design, pages 583-586, Nov. 2006.
-
(2006)
Proc. Int. Conf. Computer-Aided Design
, pp. 583-586
-
-
Choi, J.H.1
Bansal, A.2
Meterelliyoz, M.3
Murthy, J.4
Roy, K.5
-
32
-
-
47649109306
-
-
W. Shi and Z. Li. FBI: Fast buffer insertion for interconnect optimization, http://dropzone.tamu.edu/~zhuoli/GSRC/fast_buffer_insertion.html.
-
W. Shi and Z. Li. FBI: Fast buffer insertion for interconnect optimization, http://dropzone.tamu.edu/~zhuoli/GSRC/fast_buffer_insertion.html.
-
-
-
-
33
-
-
29244439390
-
On-chip power distribution grids with multiple supply volt-ages for high performance integrated circuits
-
Apr
-
M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny. On-chip power distribution grids with multiple supply volt-ages for high performance integrated circuits. In Proc. Great Lakes Symp. VLSI, pages 2-7, Apr. 2005.
-
(2005)
Proc. Great Lakes Symp. VLSI
, pp. 2-7
-
-
Popovich, M.1
Friedman, E.G.2
Sotman, M.3
Kolodny, A.4
|