Independent gate skewed logic in double-gate SOI technology

Proceedings - IEEE International SOI Conference

Volumn 2005, Issue , 2005, Pages 83-84

  Cakici, Tamer ^a   Mahmoodi, Hamid ^a   Mukhopadhyay, Saibal ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33744745861     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2005.1563543     Document Type: Conference Paper

References (5)

1. L. Change et al., Proc. of IEEE, vol. 91, pp. 1860-1873, Nov. 2003
2. D. Fried et al., IEEE EDL, vol. 24, pp. 592-594, Sep. 2003
3. L. Mathew, et al., IEEE SOI Conf., pp. 187-189, Oct. 2004
4. C. Cabral et al., Symp. on VLSI Tech., pp. 184-185, 2004
5. Taurus-DS, V2004.09, Synopsys Inc.