Fast dual-vdd buffering based on interconnect prediction and sampling

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2007, Pages 95-102

  Hu, Yu ^a   Tam, King Ho ^a   Jing, Tom Tong ^a   He, Lei ^a  

^a Engineering IV   (United States)

Author keywords

Buffer insertion; Dual V(dd); Interconnect; Low power; Routing

Indexed keywords

ALGORITHMS; DATA STRUCTURES; NETWORK ROUTING;

BUFFER INSERTION; ROUTING GRID;

INTERCONNECTION NETWORKS;

EID: 34748845673     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1231956.1231976     Document Type: Conference Paper

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