Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 9, 2005, Pages 1103-1107

  Diril, Abdulkadir Utku ^a,b   Dhillon, Yuvraj Singh ^a,c   Chatterjee, Abhijit ^d   Singh, Adit D ^e  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b NVIDIA   (United States)

^c INTEL CORPORATION   (United States)

^d GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^e AUBURN UNIVERSITY   (United States)

Author keywords

CMOS; Critical path; Low voltage; Low power design

Indexed keywords

CRITICAL PATH ANALYSIS; DIGITAL CIRCUITS; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; THRESHOLD VOLTAGE;

CMOS; CRITICAL-PATH; LOW VOLTAGE; LOW-POWER DESIGN;

CMOS INTEGRATED CIRCUITS;

EID: 27844480979     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.857149     Document Type: Review

References (14)

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