Molybdenum gate technology for ultrathin-body MOSFETs and FinFETs

IEEE Transactions on Electron Devices

Volumn 51, Issue 12, 2004, Pages 1989-1996

  Ha, Daewon ^a   Takeuchi, Hideki ^a   Choi, Yang Kyu ^b   King, Tsu Jae ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Complementary metal oxide semiconductor (CMOS); Dry etching; FinFET; Fully depleted silicon on insulator (FD SOI); Molybdenum metal gate; Sputter; Ultrathin body

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; DRY ETCHING; ELECTRODES; MOLYBDENUM; SILICA; SILICON ON INSULATOR TECHNOLOGY; SPUTTER DEPOSITION;

FINFET; FULLY DEPLETED SILICON ON INSULATOR (FD SOI); MOLYBDENUM METAL GATE; ULTRATHIN BODY;

MOSFET DEVICES;

EID: 10644265317     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.839752     Document Type: Article

References (30)

1. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, pp. 259-288, Feb. 2001.
2. M. Koh, W. Mizubayashi, K. Iwamoto, H. Murakami, T. Ono, M. Tsuno, T. Mihara, K. Shibahara, S. Miyazaki, and M. Hirose, "Limit of gate oxide thickness scaling in MOSFET due to apparent threshold voltage fluctuation induced by tunnel leakage current," IEEE Trans. Electron Devices, vol. 48, pp. 259-264, Feb. 2001.
3. International Technology Roadmap for Semiconductors. Semiconductor Industry Association. [Online]. Available: http://public.itrs.net
4. D. A. Antoniadis, "MOSFET scalability limits and "New frontier" devices," in Proc. Symp. VLSI Technology, 2002, pp. 2-5.
5. T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors," in Proc. Symp. VLSI Technology, 2000, pp. 174-175.
6. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFETs: Part I - Effects of substrate impurity concentration," IEEE Trans. Electron Devices., vol. 41, pp. 2357-2362, Dec. 1994.
7. L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, "Gate length scaling and threshold voltage control of double-gate MOSFETs," in Int. Electron Device Meet., 2000, pp. 719-722.
8. Y.-C. Yeo, Q. Lu, P. Ranade, H. Takeuchi, K. J. Yang, I. Polishchuk, T.-J. King, C. Hu, S. C. Song, H. F. Luan, and D.-L. Kwong, " Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric," IEEE Electron Device Lett., vol. 22, pp. 227-227, May 2001.
9. I. Polishchuk, P. Ranade, T.-J. King, and C. Hu, "Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion," IEEE Electron Device Lett., vol. 23, pp. 200-201, Apr. 2002.
10. J. H. Lee, H. Zhong, Y.-S. Suh, G. Heuss, J. Gurganus, B. Chen, and V. Misra, "Tunable work function dual metal gate technology for bulk and nonbulk CMOS," in Proc. Int. Electron Device Meet., 2002, pp. 359-362.
11. J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, and W. Haensch, "Metal-gate FinFET and fully depleted SOI devices using total gate silicidation," in Proc. Int. Electron Device Meet., 2002, pp. 247-250.
12. P. Ranade, Y. K. Choi, D. Ha, A. Agarwal, M. Ameen, and T.-J. King, "Tunable work function molybdenum gate technology for FDSOI-CMOS," in Proc. Int. Electron Device Meet., 2002, pp. 363-366.
13. R. J. P. Lander, J. C. Hooker, J. P. van Zijl, F. Roozeboom, M. P. M. Maas, Y. Tamminga, and R. A. M. Wolters, "A tunable metal gate work function using solid state diffusion of nitrogen," in Proc. European Solid-State Devices Res. Conf., 2002, pp. 103-106.
14. D. Ha, P. Ranade, Y. K. Choi, J.-S. Lee, T.-J. King, and C. Hu, "Molybdenum gate work function engineering for ultrathin-body silicon-on-insulator (UTB SOI) MOSFETs," Jpn. J. Appl. Phys., vol. 42, no. 4B, pp. 1979-1982, 2003.
15. Y. K. Choi, L. Chang, P. Ranade, J.-S. Lee, D. Ha, S. Balasubramanian, A. Agarwal, M. Ameen, T.-J. King, and J. Bokor, "FinFET process refinements for improved mobility and gate work function engineering," in Proc. Int. Electron Device Meet., 2002, pp. 259-262.
16. H. Takeuchi, M. She, K. Watanabe, and T.-J. King, "Damageless sputter deposition for metal gate CMOS technology," in Proc. 60th Dev. Res. Conf. , Salt Lake City, UT, 2003, pp. 35-36.
17. Y. Kuo, "Factors affecting the molybdenum line slope by reactive ion etching," J. Electrochem. Soc., vol. 137, no. 6, pp. 1907-1911, 1990.
18. 2 etching studies in inductively coupled fluorocarbon plasmas," J. Electrochem. Soc., vol. 148, no. 3, pp. C211-C221, 2001.
19. 2 mixture gas," Jpn. J. Appl. Phys., vol. 21, no. 1, pp. 168-172, 1982.
20. CRC Handbook of Chemistry and Physics (1985-1986), CRC Press, Boca Raton, FL, 1985, pp. F-178-F-178.
21. D. Ha, P. Ranade, Y. K. Choi, J.-S. Lee, T.-J. King, and C. Hu, "Ultra-thin body silicon-on-insulator (UTB SOI) MOSFET with metal gate work-function enginnering for sub-70 nm technology node," in Proc. Int. Conf. Solid-State Devices Material, 2003, pp. 782-783.
22. NJB. D. Cullity and S. R. Stock, Elements of X-Ray Diffraction, 3rd ed. Englewood Cliffs: Prentice-Hall, 2001.
23. P. Hones, N. Martin, M. Regula, and F. Levy, "Structural and mechanical properties of chromium nitride, molybdenum nitride, and tungsten nitride thin films," J. Phys. D: Appl. Phys., vol. 36, pp. 1023-1029, 2003.
24. Y. K. Choi, D. Ha, T.-J. King, and C. Hu, "Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain," IEEE Electron Device Lett., vol. 22, pp. 447-448, Sept. 2001.
25. P. E. Nicollian, W. R. Hunter, and J. C. Hu, "Experimental evidence for voltage driven breakdown models in ultrathin gate oxides," in Proc. Int. Reliability Physics Symp., 2000, pp. 7-15.
26. Y.-C. Yeo, P. Ranade, T.-J. King, and C. Hu, "Effects of high-k gate dielectric materials on metal and silicon gate work functions," IEEE Electron Device Lett., vol. 23, pp. 342-344, June 2002.
27. S. B. Samavedam, L. B. La, P. J. Tobin, B. White, C. Hobbs, L. R. C. Fonseca, A. A. Demkov, J. Schaeffer, E. Luckowski, A. Martinez, M. Raymond, D. Triyoso, D. Roan, V. Dhandapani, R. Garcia, S. G. H. Anderson, K. Moore, H. H. Tseng, C. Capasso, O. Adetutu, D. C. Gilmer, W. J. Taylor, R. Hedge, and J. Grant, "Fermi level pinning with sub-monolayer MeOx and metal gates," in Proc. Int. Electron Device Meet., 2003, pp. 307-310.
28. S. M. Rossnagel, "Sputter deposition for semiconductor manufacturing," IBM J. Res. Develop., vol. 43, no. 1/2, pp. 163-179, 1999.
29. Shred Simulation. [Online]. Available: http://nanohub.purdue.edu
30. T. Fuyuki, T. Furukawa, T. Oka, and H. Matsunami, "Deposition of high-quality silicon dioxide by remote plasma CVD technique," IEICE Trans. Electron., vol. E75-C, no. 9, pp. 1013-1018, 1992.