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Volumn , Issue , 2003, Pages 580-585

An O(nlogn) time algorithm for optimal buffer insertion

Author keywords

Buffer insertion; Data structure; Elmore delay; Routing

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DATA STRUCTURES; ROUTERS;

EID: 0041633712     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775832.775980     Document Type: Conference Paper
Times cited : (35)

References (9)
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  • 3
    • 0031384628 scopus 로고    scopus 로고
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    • (1997) ICCAD , pp. 707-712
    • Kang, M.1    Dai, W.W.-M.2    Dillinger, T.3    LaPotin, D.4
  • 4
    • 0030110490 scopus 로고    scopus 로고
    • Optimal wire sizing and buffer insertion for low power and a generalized delay model
    • J. Lillis, C. K. Cheng and T.-T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," IEEE Trans. Solid-State Circuits 31(3), 1996, 437-447.
    • (1996) IEEE Trans. Solid-State Circuits , vol.31 , Issue.3 , pp. 437-447
    • Lillis, J.1    Cheng, C.K.2    Lin, T.-T.Y.3
  • 5
    • 0029712263 scopus 로고    scopus 로고
    • New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing
    • J. Lillis, et. al., "New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing," DAC 1996, 359-400.
    • (1996) DAC , pp. 359-400
    • Lillis, J.1
  • 6
    • 0030410359 scopus 로고    scopus 로고
    • Buffered Steiner tree construction with wire sizing for interconnect layout optimization
    • T. Okamoto and J. Cong, "Buffered Steiner tree construction with wire sizing for interconnect layout optimization," ICCAD 1996, 44-49.
    • (1996) ICCAD , pp. 44-49
    • Okamoto, T.1    Cong, J.2
  • 7
    • 0030379336 scopus 로고    scopus 로고
    • A fast algorithm for area minimization of slicing floorplans
    • W. Shi, "A fast algorithm for area minimization of slicing floorplans," IEEE Trans. CAD 15(6), 1996, 550-571.
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    • Shi, W.1
  • 8
    • 0025594311 scopus 로고
    • Buffer placement in distributed RC-tree network for minimal Elmore delay
    • L. P. P. P. van Ginneken, "Buffer placement in distributed RC-tree network for minimal Elmore delay," ISCAS 1990, 865-868.
    • (1990) ISCAS , pp. 865-868
    • Van Ginneken, L.P.P.P.1
  • 9
    • 0034229328 scopus 로고    scopus 로고
    • Simultaneous routing and buffer insertion with restrictions on buffer locations
    • H. Zhou, D. F. Wong, I. M. Liu and A. Aziz, "Simultaneous routing and buffer insertion with restrictions on buffer locations," IEEE Trans. CAD 19(7), 2000, 819-824.
    • (2000) IEEE Trans. CAD , vol.19 , Issue.7 , pp. 819-824
    • Zhou, H.1    Wong, D.F.2    Liu, I.M.3    Aziz, A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.