-
1
-
-
4444302686
-
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era
-
DAC 2004, San Diego, CA
-
A. Basu, S.-C. Lin, V. Wason, A. Mehrotra and K. Banerjee, "Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era," Proc. Design Automation Conference, DAC 2004, San Diego, CA, pp 884-887, 2004.
-
(2004)
Proc. Design Automation Conference
, pp. 884-887
-
-
Basu, A.1
Lin, S.-C.2
Wason, V.3
Mehrotra, A.4
Banerjee, K.5
-
2
-
-
0029293575
-
Minimizing power consumption in digital CMOS circuits
-
A. P. Chandrakasan and R. W. Brodersen, "Minimizing Power Consumption in Digital CMOS Circuits," Proceedings of the IEEE, vol. 83(4), pp. 498-523, 1995.
-
(1995)
Proceedings of the IEEE
, vol.83
, Issue.4
, pp. 498-523
-
-
Chandrakasan, A.P.1
Brodersen, R.W.2
-
3
-
-
1642373108
-
Design guideline of an ultra-thin body SOI MOSFET for low-power and high-performance applications
-
X. An, R. Huang, B. Zhao, X. Zhang and Y. Wang, "Design Guideline of an Ultra-Thin Body SOI MOSFET for Low-Power and High-Performance Applications," Semiconductor Science and Technology, vol. 19(3), pp. 347-350, 2004.
-
(2004)
Semiconductor Science and Technology
, vol.19
, Issue.3
, pp. 347-350
-
-
An, X.1
Huang, R.2
Zhao, B.3
Zhang, X.4
Wang, Y.5
-
4
-
-
79956033267
-
Direct tunneling leakage current and scalability of alternative gate dielectrics
-
Y.-C. Yeo, T.-J. King and C. Hu, "Direct Tunneling Leakage Current and Scalability of Alternative Gate Dielectrics," Applied Physics Letters, vol. 81(11), pp. 2091-2093, 2002.
-
(2002)
Applied Physics Letters
, vol.81
, Issue.11
, pp. 2091-2093
-
-
Yeo, Y.-C.1
King, T.-J.2
Hu, C.3
-
5
-
-
0037965994
-
Direct tunneling from source to drain in nanometer-scale silicon transistors
-
H. Kawaura and T. Baba, "Direct Tunneling from Source to Drain in Nanometer-Scale Silicon Transistors," Japanese Journal of Applied Physics, vol. 42, Part 1(2A), pp. 351-357, 2003.
-
(2003)
Japanese Journal of Applied Physics
, vol.42
, Issue.1-2 PART AND A
, pp. 351-357
-
-
Kawaura, H.1
Baba, T.2
-
6
-
-
0031275325
-
Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects
-
K. Chen, C. Hu, P. Fang, M. R. Lin and D. L. Wollesen, "Predicting CMOS Speed with Gate Oxide and Voltage Scaling and Interconnect Loading Effects," IEEE Transactions on Electron Devices, vol. 44(11), pp. 1951-1957, 1997.
-
(1997)
IEEE Transactions on Electron Devices
, vol.44
, Issue.11
, pp. 1951-1957
-
-
Chen, K.1
Hu, C.2
Fang, P.3
Lin, M.R.4
Wollesen, D.L.5
-
7
-
-
0031143076
-
Back-gated CMOS on SOIAS for dynamic threshold voltage control
-
I. Y. Yang, C. Vieri, A. Chandrakasan and D. A. Antoniadis, "Back-Gated CMOS on SOIAS for Dynamic Threshold Voltage Control," IEEE Transactions on Electron Devices, vol. 44(5), pp. 822-831, 1997.
-
(1997)
IEEE Transactions on Electron Devices
, vol.44
, Issue.5
, pp. 822-831
-
-
Yang, I.Y.1
Vieri, C.2
Chandrakasan, A.3
Antoniadis, D.A.4
-
8
-
-
0346499659
-
Back-gated MOSFETs with controlled silicon thickness for adaptive threshold-voltage control
-
U. Avci and S. Tiwari, "Back-Gated MOSFETs with Controlled Silicon Thickness for Adaptive Threshold-Voltage Control," Electronics Letters, vol. 40(1), pp. 74-75, 2004.
-
(2004)
Electronics Letters
, vol.40
, Issue.1
, pp. 74-75
-
-
Avci, U.1
Tiwari, S.2
-
9
-
-
84939180950
-
SB-IGFET: An insulated-gate field-effect transistor using schottky barrier contacts for source and drain
-
T. Lepselter and S. M. Sze, "SB-IGFET: An Insulated-Gate Field-Effect Transistor using Schottky Barrier Contacts for Source and Drain," Proceedings of the IEEE, vol. 56, pp. 1400-1401, 1968.
-
(1968)
Proceedings of the IEEE
, vol.56
, pp. 1400-1401
-
-
Lepselter, T.1
Sze, S.M.2
-
10
-
-
0037672096
-
Schottky source/drain SOI MOSFET with shallow doped extension
-
M. Nishisaka, S. Matsumoto and T. Asano, "Schottky Source/Drain SOI MOSFET with Shallow Doped Extension," Japanese Journal Applied Physics, vol. 42, Part 1(4B), pp. 2009-2013, 2003.
-
(2003)
Japanese Journal Applied Physics
, vol.42
, Issue.1-4 PART AND B
, pp. 2009-2013
-
-
Nishisaka, M.1
Matsumoto, S.2
Asano, T.3
-
11
-
-
0037806771
-
Nano-scale implantless schottky-barrier SOI FinFETs with excellent ambipolar performance
-
H.-C. Lin, M.-F. Wang, F.-J. Hou, J.-T. Liu, F.-H. Ko, H.-L. Chen, G.-W. Huang, T.-Y. Huang and S. M. Sze, "Nano-Scale Implantless Schottky-Barrier SOI FinFETs with Excellent Ambipolar Performance," Proc. 60th Device Research Conference, DRC2002, pp 45-46, 2002.
-
(2002)
Proc. 60th Device Research Conference, DRC2002
, pp. 45-46
-
-
Lin, H.-C.1
Wang, M.-F.2
Hou, F.-J.3
Liu, J.-T.4
Ko, F.-H.5
Chen, H.-L.6
Huang, G.-W.7
Huang, T.-Y.8
Sze, S.M.9
-
13
-
-
0032257711
-
Comparison of raised and schottky source/drain MOSFETs using a novel tunneling contact model
-
San Francisco, CA, USA
-
M. Ieong, P. M. Solomon, S. E. Laux, H.-S. P. Wong and D. Chidambarrao, "Comparison of Raised and Schottky Source/Drain MOSFETs Using a Novel Tunneling Contact Model," Proc. International Electron Devices Meeting, IEDM '98, San Francisco, CA, USA, pp 733-736, 1998.
-
(1998)
Proc. International Electron Devices Meeting, IEDM '98
, pp. 733-736
-
-
Ieong, M.1
Solomon, P.M.2
Laux, S.E.3
Wong, H.-S.P.4
Chidambarrao, D.5
-
14
-
-
0032284102
-
Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
-
San Francisco, CA, USA
-
H.-S. P. Wong, D. J. Frank and P. M. Solomon, "Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gated Ultra-Thin SOI MOSFET's at the 25 nm Channel Length Generation," Proc. International Electron Devices Meeting, IEDM '98, San Francisco, CA, USA, pp 407-410, 1998.
-
(1998)
Proc. International Electron Devices Meeting, IEDM '98
, pp. 407-410
-
-
Wong, H.-S.P.1
Frank, D.J.2
Solomon, P.M.3
-
15
-
-
0025482231
-
Subthreshold slope in thin-film SOI MOSFETs
-
D. J. Wouters, J.-P. Colinge and H. E. Maes, "Subthreshold Slope in Thin-Film SOI MOSFETs," IEEE Transactions on Electron Devices, vol. 37(9), pp. 2022-2033, 1990.
-
(1990)
IEEE Transactions on Electron Devices
, vol.37
, Issue.9
, pp. 2022-2033
-
-
Wouters, D.J.1
Colinge, J.-P.2
Maes, H.E.3
-
16
-
-
0036923594
-
Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation
-
J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong and W. Haensch, "Metal-Gate FinFET and Fully-Depleted SOI Devices using Total Gate Silicidation," Proc. International Electron Devices Meeting, IEDM '02, pp 247-250, 2002.
-
(2002)
Proc. International Electron Devices Meeting, IEDM '02
, pp. 247-250
-
-
Kedzierski, J.1
Nowak, E.2
Kanarsky, T.3
Zhang, Y.4
Boyd, D.5
Carruthers, R.6
Cabral, C.7
Amos, R.8
Lavoie, C.9
Roy, R.10
Newbury, J.11
Sullivan, E.12
Benedict, J.13
Saunders, P.14
Wong, K.15
Canaperi, D.16
Krishnan, M.17
Lee, K.-L.18
Rainey, B.A.19
Fried, D.20
Cottrell, P.21
Wong, H.-S.P.22
Ieong, M.23
Haensch, W.24
more..
-
18
-
-
0038009941
-
Investigation of gate-induced drain leakage (GIDL) current in thin body devices: Single-gate ultra-thin body, symmetrical double-gate, and asymmetrical double-gate MOSFETs
-
Y.-K. Choi, D. Ha, T.-J. King and J. Bokor, "Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs," Japanese Journal Applied Physics, vol. 42, Part 1(4B), pp. 2073-2076, 2003.
-
(2003)
Japanese Journal Applied Physics
, vol.42
, Issue.1-4 PART AND B
, pp. 2073-2076
-
-
Choi, Y.-K.1
Ha, D.2
King, T.-J.3
Bokor, J.4
-
19
-
-
0034453418
-
Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime
-
San Francisco, CA, USA
-
J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King and C. Hu, "Complementary Silicide Source/Drain Thin-Body MOSFETs for the 20 nm Gate Length Regime," Proc. International Electron Devices Meeting, IEDM2000, San Francisco, CA, USA, pp 57-60, 2000.
-
(2000)
Proc. International Electron Devices Meeting, IEDM2000
, pp. 57-60
-
-
Kedzierski, J.1
Xuan, P.2
Anderson, E.H.3
Bokor, J.4
King, T.-J.5
Hu, C.6
-
20
-
-
12844273425
-
Spatial computation
-
Boston, MA
-
M. Budiu, G. Venkataramani, T. Chelcea and S. C. Goldstein, "Spatial Computation," Proc. International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS'04, Boston, MA, 2004.
-
(2004)
Proc. International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS'04
-
-
Budiu, M.1
Venkataramani, G.2
Chelcea, T.3
Goldstein, S.C.4
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