Exploring high-dimensional topologies for NoC design through an integrated analysis and synthesis framework

Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008

Volumn , Issue , 2008, Pages 107-116

  Gilabert, F ^a   Medardoni, S ^a   Bertozzi, D ^a   Benini, L ^b   Gomez, M E ^c   Lopez, P ^c   Duato, J ^c  

^a UNIVERSITY OF FERRARA   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION BANDWIDTH; CONCENTRATED TOPOLOGIES; NETWORKS-ON-CHIP (NOC);

BANDWIDTH; COMPUTER SIMULATION; MESH GENERATION; SYNCHRONIZATION; TELECOMMUNICATION TRAFFIC;

MICROPROCESSOR CHIPS;

EID: 44149116785     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2008.4492730     Document Type: Conference Paper

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