A distributed multi-point network interface for low-latency, deadlock-free on-chip interconnects

2006 1st International Conference on Nano-Networks and Workshops, Nano-Net

Volumn , Issue , 2006, Pages

  Park, Dongkook ^a   Nicopoulos, Chrysostomos ^a   Kim, Jongman ^a   Vijaykrishnan, N ^a   Das, Chita R ^a  

^a The Pennsylvania State University   (United States)

Author keywords

Deadlock; Network on chip; Router design; Topology

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BIOLOGICAL MATERIALS; CHLORINE COMPOUNDS; ELECTRIC LOAD FORECASTING; ELECTRIC NETWORK TOPOLOGY; ENERGY POLICY; INJECTION (OIL WELLS); INTEGRATED CIRCUITS; INTERFACES (COMPUTER); OPTICAL INTERCONNECTS; PROGRAMMABLE LOGIC CONTROLLERS; TELECOMMUNICATION NETWORKS; TOPOLOGY;

ARCHITECTURAL IMPROVEMENTS; AREA OVERHEAD; COMPLEX ALGORITHMS; COMPLEX SYSTEMS; CYCLE-ACCURATE SIMULATION; DEADLOCK; DEADLOCK AVOIDANCE; ENERGY CONSUMPTION; FEATURE SIZES; HUNGRY ALGORITHMS; INTERNATIONAL CONFERENCES; LOW-LATENCY; MESH NETWORK TOPOLOGIES; NANO-NET; NANO-NETWORKS; NETWORK INFRASTRUCTURES; NETWORK INTERFACE CONTROLLERS; NETWORK INTERFACES; NETWORK LATENCIES; NETWORK-ON-CHIP; ON-CHIP INTERCONNECTS; ON-CHIP SYSTEMS; POWER CONSUMPTION; RESOURCE-CONSTRAINED; ROUTER DESIGN;

ROUTERS;

EID: 50149098445     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANONET.2006.346214     Document Type: Conference Paper

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