Cost-performance trade-offs in networks on chip: A simulation-based approach

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 764-769

  Pestana, Santiago Gonzalez ^a   Rijpkema, Edwin ^a   Rǎdulescu, Andrei ^a   Goossens, Kees ^a   Gangwal, Om Prakash ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK LATENCY; NETWORKS ON CHIP (NOC); PERFORMANCE METRICS; RUN-TIME NETWORK INSTANTIATION; COST PERFORMANCE; IN NETWORKS; NETWORK TOPOLOGY; NETWORK-BASED; NETWORKS ON CHIPS; SIMULATION ENVIRONMENT; SYSTEMS ON CHIPS;

COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS; INTERFACES (COMPUTER); ROUTERS; XML; COSTS; DESIGN; ECONOMIC AND SOCIAL EFFECTS; EXHIBITIONS; TELECOMMUNICATION NETWORKS;

VLSI CIRCUITS; MICROPROCESSOR CHIPS;

EID: 3042558166     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268972     Document Type: Conference Paper

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