Early wire characterization for predictable network-on-chip global interconnects

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2007, Pages 57-64

  Hatirnaz, Ilhan ^a   Badel, Stephane ^a   Pazos, Nuria ^a   Leblebici, Yusuf ^a   Murali, Srinivasan ^b   Atienza, David ^c   De Micheli, Giovanni ^c  

^a Ceramics Laboratory Ecole Polytechnique Federale de Lausanne   (Switzerland)

^b STANFORD UNIVERSITY   (United States)

^c EPFL   (Switzerland)

Author keywords

Design methodology; Early wire characterization; Global interconnects; NoCs

Indexed keywords

INTEGRATED CIRCUITS; NANOTECHNOLOGY;

DESIGN METHODOLOGY; EARLY WIRE CHARACTERIZATION; GLOBAL INTERCONNECTS; NETWORK-ON-CHIP;

INTERCONNECTION NETWORKS;

EID: 34748848586     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1231956.1231969     Document Type: Conference Paper

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