NoC design and implementation in 65nm technology

Proceedings - NOCS 2007: First International Symposium on Networks-on-Chip

Volumn , Issue , 2007, Pages 273-282

  Pullini, Antonio ^a   Angiolini, Federico ^b   Meloni, Paolo ^c   Atienza, David ^d,e   Murali, Srinivasan ^f   Raffo, Luigi ^c   De Micheli, Giovanni ^d   Benini, Luca ^b  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

^c UNIVERSITY OF CAGLIARI   (Italy)

^d EPFL   (Switzerland)

^e UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^f STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; SCALABILITY;

EMBEDDED COMPUTING; NETWORKS-ON-CHIP (NOC); ON-CHIP COMPUTATION BLOCKS; TRADEOFFS;

MICROPROCESSOR CHIPS;

EID: 36348968825     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2007.30     Document Type: Conference Paper

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