Mesh routing topologies for multi-FPGA systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 3, 1998, Pages 400-408

  Hauck, Scott ^a,b   Bordello, Gaetano ^a,c   Ebeling, Carl ^a,c  

^a IEEE   (United States)

^b Northwestern University   (United States)

^c University of Washington   (United States)

Author keywords

Computer aided design; Gate array; Microelectronics; Reconfigurable computing; Routing

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MICROELECTRONICS; ROUTERS;

MESH ROUTING TOPOLOGY; RECONFIGURABLE COMPUTING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032167140     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.711311     Document Type: Article

References (22)

1. Aptix Corporation, Data Book, San Jose, CA, Feb. 1993.
2. J. Babb, R. Tessier, and A. Agarwal, "Virtual wires: Overcoming pin limitations in FPGA-based logic emulators," in Proc. IEEE Workshop FPGA's Custom Computing Machines, 1993, pp. 142-151.
3. P. K. Chan and M. D. F. Schlag, "Architectural tradeoffs in field-programmable-device-based computing systems," in Proc. IEEE Workshop FPGA's Custom Computing Machines, 1993, pp. 152-161.
4. C. P. Cowen and S. Monaghan, "A reconfigurable Monte-Carlo clustering processor (MCCP)," in Proc. IEEE Workshop FPGA's Custom Computing Machines, 1994, pp. 59-65.
5. S. A. Cuccaro and C. F. Reese, "The CM-2X: A hybrid CM-2/Xilinx prototype," in Proc. IEEE Workshop FPGA's Custom Computing Machines, 1993, pp. 121-130.
6. M. Gokhale, B. Holmes, A. Kopser, D. Kunze, D. Lopresti, S. Lucas, R. Minnich, and P. Olsen, "Splash: A reconfigurable linear logic array," in Proc. Int. Conf. Parallel Processing, 1990, pp. 526-532.
7. S. Hauck, "Multi-FPGA systems," Ph.D. dissertation, Univ. Washington, Dept. Comput. Sci. Eng., 1995.
8. S. Hauck and G. Borriello, "Pin assignment for multi-FPGA systems," IEEE Trans. Computer-Aided Design, vol. 16, pp. 956-964, Sept. 1997.
9. D. T. Hoang, "Searching genetic databases on splash 2," in Proc. IEEE Workshop FPGA's Custom Computing Machines, 1993, pp. 185-191.
10. H. Högl, A. Kugel, J. Ludvig, R. Männer, K. H. Noffz, and R. Zoz, "Enable++: A second generation FPGA processor," in Proc. IEEE Symp. FPGA's Custom Computing Machines, 1995.
11. N. Howard, A. Tyrrell, and N. Allinson, "FPGA acceleration of electronic design automation tasks," in More FPGAs, W. R. Moore and W. Luk,Eds. Oxford, U.K.: Abingdon EE&CS Books, 1994, pp. 337-344.
12. I-Cube, Inc., The FPID Family Data Sheet, Santa Clara, CA, Feb. 1994.
13. E. Lemoine and D. Merceron, "Run time reconfiguration of FPGA for scanning genomic databases," in Proc. IEEE Symp. FPGA's Custom Computing Machines, 1995.
14. L. E. McMurchie and C. Ebeling, "PathFinder: A negotiation-based performance-driven router for FPGA's," in Proc. ACM/SIGDA Int. Symp. Field Programmable Gate Arrays, 1995, pp. 111-117.
15. L. Moll, J. Vuillemin, and P. Boucard, "High-energy physics on DECPeRLe-1 programmable active memory," in Proc. ACM/SIGDA Int. Symp. Field-Programmable Gate Arrays, 1995, pp. 47-52.
16. S. Monaghan and C. P. Cowen, "Reconfigurable multi-bit processor for DSP applications in statistical physics," in Proc. IEEE Workshop FPGA's Custom Computing Machines, 1993, pp. 103-110.
17. H. Schmit and D. Thomas, "Implementing hidden Markov modeling and fuzzy controllers in FPGA's," in Proc. IEEE Symp. FPGA's Custom Computing Machines, 1995.
18. S. D. Scott, A. Samal, and S. Seth, "HGA: A hardware-based genetic algorithm," in Proc. ACM/SIGDA Int. Symp. Field-Programmable Gate Arrays, 1995, pp. 53-59.
19. C. Selvidge, A. Agarwal, M. Dahl, and J. Babb, "TIERS: Topology independent pipelined routing and scheduling for virtualwire™ compilation," in Proc. ACM/SIGDA Int. Symp. Field-Programmable Gate Arrays, 1995, pp. 25-31.
20. J. Varghese, M. Butts, and J. Batcheller, "An efficient logic emulation system," IEEE Trans. VLSI Syst., vol. 1, pp. 171-174, June 1993.
21. J. Vuillemin, P. Bertin, D. Roncin, M. Shand, H. Touati, and P. Boucard, "Programmable active memories: Reconfigurable systems come of age," IEEE Trans. VLSI Syst., 1995.
22. The Programmable Gate Array Data Book, San Jose, CA: Xilinx, Inc., 1992.