Variation

IEEE Transactions on Semiconductor Manufacturing

Volumn 21, Issue 1, 2008, Pages 63-70

  Balakrishnan, Karthik ^a   Cai, Hong ^b   Drego, Nigel ^a   Farahanchi, Ali ^a   Gettings, Karen M ^c   Lim, Daihyun ^a   Somani, Ajay ^d   Taylor, Hayden ^a   Truque, Daniel ^e   Xie, Xiaolin ^b  

^a Massachusetts Institute of Technology   (United States)

^b Goldman Sachs Group   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d Susquehanna International Group LLP   (United States)

^e MCKINSEY AND COMPANY   (United States)

Author keywords

Design for manufacturability (DFM); Statistical process control; Variation; Yield

Indexed keywords

FEEDBACK CONTROL; FEEDFORWARD CONTROL; MEASUREMENT THEORY; ROBUSTNESS (CONTROL SYSTEMS); STATISTICAL PROCESS CONTROL;

DESIGN FOR MANUFACTURABILITY (DFM); VARIATION;

INTEGRATED CIRCUITS;

EID: 38949142594     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2007.913194     Document Type: Conference Paper

References (36)

1. S. R. Nassif, "Design for variability in DSM technologies," in Proc. Int. Symp. Quality Electronic Design, 2000, pp. 451-454.
2. D. Boning, K. Balakrishnan, H. Cai, N. Drego, A. Farahanchi, K. Gettings, D. Lim, A. Somani, H. Taylor, D. Truque, and X. Xie, "Variation," in Proc. Int. Symp. Quality Electronic Design, Mar. 2007, pp. 15-20.
3. D. Bartelink, "Statistical metrology: At the root of manufacturing control," J. Vacuum Sci. Tech. B, vol. 12, no. 4, pp. 2785-2794, Jul. 1994.
4. D. Boning, A. Diebold, Ed., "Statistical metrology, with applications to interconnect and yield modeling," in Handbook of Silicon Semiconductor Metrology. New York: Marcel Dekker, 2001.
5. T. Smith, S. J. Fang, J. A. Stefani, G. B. Shinn, D. S. Boning, and S. W. Butler, "On-line patterned wafer thickness control of chemical-mechanical polishing," J. Vacuum Sci. Tech. A, vol. 17, no. 4, pp. 1384-1390, Jul. 1999.
6. B. Stine, D. Ouma, R. Divecha, D. Boning, J. Chung, D. Hetherington, C. R. Harwood, O. S. Nakagawa, and S.-Y. Oh, "Rapid characterization and modeling of pattern dependent variation in chemical mechanical polishing," IEEE Trans. Semicond. Manuf., vol. 11, no. 1, pp. 129-140, Feb. 1998.
7. D. O. Ouma, D. S. Boning, J. E. Chung, W. G. Easter, V. Saxena, S. Misra, and A. Crevasse, "Characterization and modeling of oxide chemical mechanical polishing using planarization length and pattern density concepts," IEEE Trans. Semicond. Manuf., vol. 15, no. 2, pp. 232-244, May 2002.
8. T. Tugbawa, T. Park, and D. Boning, "Integrated chip-scale simulation of pattern dependencies in copper electroplating and copper chemical mechanical polishing processes," in Proc. Int. Interconnect Tech. Conf., Jun. 2002, pp. 167-169.
9. H. Cai, H. T. Park, D. Boning, Y. Kang, J. Lee, S. K. Kim, and H. Kim, "Coherent chip-scale modeling for copper CMP pattern dependence," in Proc. CMP Symp., MRS Spring Meeting, Apr. 2004.
10. T. Park, T. Tugbawa, D. Boning, C. Chidambaram, C. Borst, and G. Shin, "Chip-scale modeling of electroplated copper surface profiles," J. Electrochem. Soc., vol. 151, pp. C418-C430, Jun. 2004.
11. K. O. Abrokwah, P. R. Chidambaram, and D. S. Boning, "Pattern based prediction for plasma etch," IEEE Trans. Semiconduct. Manuf., vol. 20, no. 2, pp. 77-86, May 2007.
12. H. K. Taylor, H. Sun, T. F. Hill, A. Farahanchi, and D. S. Boning, "Characterizing and predicting spatial non-uniformity in the deep reactive ion etching of silicon," J. Electrochem. Soc., vol. 153, pp. C575-C585, Jun. 2006.
13. W. Grobman, M. Thompson, R. Wang, C. Yuan, R. Tian, and E. Demircan, "Retical enhancement technology: Implications and challenges for physical design," in Proc. Design Automation Conf., 2001, pp. 73-78.
14. M. Orshansky, L. Milor, and C. Hu, "Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction," IEEE Trans. Semiconduct. Manuf., vol. 17, no. 1, pp. 2-11, Feb. 2004.
15. D. Boning and S. Nassif, A. Chandrakasan, W. Bowhill, and F. Fox, Eds., "Models of process variations in device and interconnect," in Design of High Performance Microprocessor Circuits. Piscataway, NJ: IEEE Press, 2000.
16. A. Srivastava, D. Sylvester, and D. Blaauw, Statistical Analysis and Optimization for VLSI: Timing and Power. New York: Springer, 2005.
17. B. Stine, D. Boning, and J. Chung, "Analysis and decomposition of spatial variation in integrated circuit processes and devices," IEEE Trans. Semiconduct. Manuf., vol. 10, no. 1, pp. 24-41, Feb. 1997.
18. S. R. Nassif, "Model to hardware matching for nanometer scale technologies," in Proc. Int. Symp. Low Power Electronic Design, 2006, pp. 203-206.
19. D. Boning, J. Panganiban, K. Gonzalez-Valentin, S. Nassif, C. Mc-Dowell, A. Gattiker, and F. Liu, "Test structures for delay variability," in Proc. ACM/IEEE Int. Workshop Timing Issues Specification Synthesis of Digital Systems TAU 2002, Monterey, CA, Dec. 2002, p. 109.
20. L.-T. Pang and B. Nikolic, "Impact of layout on 90 nm CMOS process parameter fluctuations," Proc. Symp. VLSI Circuits, pp. 69-70, 2006.
21. M. Bhushan, M. B. Ketchen, S. Polonksy, and A. Gattiker, "Ring oscillator based technique for measuring variability statistics," in Proc. Int. Conf. Microelectronic Test Structures, 2006, pp. 87-92.
22. K. Gettings and D. Boning, "Test circuit for study of CMOS process variation by measurement of analog characteristics," in Proc. Int. Conf. Microelectronic Test Structures, 2007, pp. 37-41.
23. N. Drego, A. Chandrakasan, and D. Boning, "A test-structure to efficiently study threshold-voltage variation in large MOSFET arrays," in Proc. Int. Symp. Quality Electronic Design, Mar. 2007, pp. 281-286.
24. B. Stine, D. Boning, J. Chung, L. Camilletti, F. Kruppa, E. Equi, W. Loh, S. Prasad, M. Muthukrishnan, D. Towery, M. Berman, and A. Kapoor, "The physical and electrical effects of metal fill patterning practices for oxide chemical mechanical polishing processes," IEEE Trans. Electron. Dev., vol. 45, no. 3, pp. 665-679, Mar. 1998.
25. K. Y. Tong, V. Kheterpal, V. Rovner, L. Pileggi, and H. Schmit, "Regular logic fabrics for a via patterned gate array (VPGA)," in Proc. Custom Integrated Circuit Conf., 2003, pp. 53-56.
26. V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, A. J. Strojwas, and L. Pileggi, "Design methodology for IC manufacturability based on regular logic-bricks," in Proc. Design Automation Conf., 2005, pp. 235-358.
27. M. Lavin, F.-L. Heng, and G. Northrop, "Backend CAD flows for 'restrictive design rules'," in Proc. Int. Conf. Computer Aided Design, Nov. 2004, pp. 739-746.
28. R. Montoye, W. Belluomini, H. Ngo, C. McDowell, J. Sawada, T. Nguyen, B. Veraa, J. Wagoner, and M. Lee, "A double precision floating-point multiplier," in Proc. Int. Solid State Circuits Conf., 2003.
29. M. Gazor, "Design for manufacturability with regular fabrics in digital integrated circuits," S.M. thesis, Dept. Electrical Engineering and Computer Science, MIT, Cambridge, May 2005.
30. D. Lim, J. Kim, J.-O. Plouchart, C. Cho, D. Kim, R. Trzcinski, and D. Boning, "Performance variability of a 100 GHz static CML frequency divider in 65nm SOI CMOS technology," in Proc. Int. Solid State Circuits Conf., Feb. 2007, pp. 542-543.
31. D. Lim, J. Kim, D. Kim, C. Cho, and D. Boning, "Performance and yield optimization of mm-wave PLL front-end in 65 nm SOI CMOS," in Proc. Radio Frequency Integrated Circuits Symp., 2007, pp. 525-538.
32. C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, and D. A. B. Miller, "Receiver-less optical clock injection for clock distribution networks," IEEE J. Select. Topics Quantum Electron., vol. 9, no. 2, pp. 400-409, 2003.
33. K. Balakrishnan, "Analysis of variation in on-chip waveguide distribution schemes and optical receiver circuits," S.M. thesis, Dept. Electrical Engineering and Computer Science, MIT, Cambridge, 2006.
34. A. Agarwal, D. Blaauw, and V. Zolotov, "Statistical timing analysis for intra-die process variations with, spatial correlations," in Proc. Int. Conf. Computer Aided Design, Nov. 2003, pp. 900-907.
35. A. Kurokawa, T. Kanamoto, T. Ibe, A. Kasebe, C. W. Fong, T. Kage, Y. Inoue, and H. Masuda, "Dummy filling methods for reducing interconnect capacitance and number of fills," in Proc. Int. Symp. Quality Electronic Design, 2005, pp. 586-591.
36. A. B. Kahng, K. Samadi, and P. Sharma, "Study of floating fill impact on interconnect capacitance," in Proc. Int. Symp. Quality Electronic Design, 2006, pp. 691-696.