Design for variability in DSM technologies

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2000-January, Issue , 2000, Pages 451-454

  Nassif, Sani R ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUITS; WIRE;

DEEP SUB-MICRON; DESIGN FOR VARIABILITIES; FABRICATION PROCESS; HISTORICAL TRENDS; PROCESS VARIABILITY; WIRE PARAMETERS; WITHIN-DIE VARIATIONS; WORST CASE DESIGN;

DIES;

EID: 84950107446     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2000.838919     Document Type: Conference Paper

References (15)

1. S. W. Director and W. Maly, editors. Statistical Approach to VLSI, volume 8 of Advances in CAD for VLSI. North-Holland, 1994.
2. J. Power, B. Donnellan, A. Mathewson, and W. Lane. Relating statistical mosfet model parameter variabilities to ic manufacturing process fluctuations enabling realistic worst case design. IEEE Trans. Semiconductor Manufacturing, Aug. 1994.
3. A. Misaka, A. Goda, K. Matsuoka, H. Umimoto, and S. Odanaka. A statistical critical dimension control at cmos cell level. In Proceedings of IEDM, 1996.
4. S. R. Nassif. Within-chip variability analysis. In Proceedings of IEDM, 1998.
5. M. Eisele, J. Berthold, D. Schmitt-Landseidel, and R. Mahnkopf. The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Trans. VLSI, Dec. 1997.
6. The National Technology Roadmap for Semiconductors, 1997.
7. C. Alpert, A. Devghan, and S. Quay. Buffer insertion with accurate models for gate and interconnect delay. In Proceedings of DAG, 1999.
8. V. Mehrotra, S. Nassif, D. Boning, and J. Chung. Modeling the effects of manufacturing variations on high-speed microprocessor interconnect performance. In Proceedings of IEDM, 1998.
9. R. Spence and R. S. Soin. Tolerance Design of Electronic Circuits. Addison-Wesley, 1988.
10. J. C. Zhang and M. A. Styblinski. Yield Vanablity Optimization of Integrated Circuits. Kluwer, 1995.
11. A. J. Strojwas, S. R. Nassif, and S. W. Director. A methodology for worst case design of integrated circuits. In Proceedings of IEEE ICCAD, 1983.
12. M. Bolt, M. Rocchi, and J. Engel. Realistical statistical worst-case simulations of vlsi circuits. IEEE Trans. Semiconductor Manufacturing, Aug. 1991.
13. L. W. Nagel. SPICES: A Computer Program to Simulate Semiconductor Circuits. PhD thesis, University of California, Berkeley, 1975.
14. B. E. Stine, D. S. Boning, and J. E. Chung. Analysis and decomposition of spatial variation in integrated circuit processes and devices. IEEE Trans. Semiconductor Manufacturing, Feb. 1997.
15. V. Mehrotra, S. Sam, D. Boning, A. Chandrakanan, R. Vallishayee, and S. Nassif. A methodology for modeling the effects of systematic process variations on circuit performance. Submitted to DAC 2000.