-
1
-
-
0038642569
-
An integrated test Chip: For the complete characterization and monitoring of a 0.25um-CMOS technology that fits into five-scribe-line structures 150um by 5,000um
-
Mar
-
R. Lefferts and C. Jakubiec, "An integrated test Chip: for the complete characterization and monitoring of a 0.25um-CMOS technology that fits into five-scribe-line structures 150um by 5,000um," International Conference on Microelectronic test Structures pp. 59-63, Mar. 2003.
-
(2003)
International Conference on Microelectronic test Structures
, pp. 59-63
-
-
Lefferts, R.1
Jakubiec, C.2
-
2
-
-
33745787679
-
-
Master's thesis, MIT, Cambridge, MA, Available through MIT Libraries, Institute Archives Microforms, Noncirculating Collection 3, Cambridge, MA
-
K. M. González-Valentin, "Extraction of variation sources due to layout practices," Master's thesis, MIT, Cambridge, MA, 2002. Available through MIT Libraries, Institute Archives Microforms, Noncirculating Collection 3, Cambridge, MA.
-
(2002)
Extraction of variation sources due to layout practices
-
-
González-Valentin, K.M.1
-
3
-
-
0038177368
-
-
Master's Thesis, MIT, Cambridge, MA, Available through MIT Libraries, Institute Archives Microforms, Noncirculating Collection 3, Cambridge, MA
-
J. S. Panganiban, "A Ring-Oscillator-Based Variation Test Chip," Master's Thesis, MIT, Cambridge, MA, 2002., Available through MIT Libraries, Institute Archives Microforms, Noncirculating Collection 3, Cambridge, MA.
-
(2002)
A Ring-Oscillator-Based Variation Test Chip
-
-
Panganiban, J.S.1
-
4
-
-
33747070284
-
Ring Oscillator Based Technique for Measuring Variability Statistics
-
Mar
-
M. Bhushan, M. B. Ketchen, S. Polonsky, and A. Gattiker, "Ring Oscillator Based Technique for Measuring Variability Statistics," International Conference on Microelectronic Test Structures, pp. 87-92, Mar. 2006.
-
(2006)
International Conference on Microelectronic Test Structures
, pp. 87-92
-
-
Bhushan, M.1
Ketchen, M.B.2
Polonsky, S.3
Gattiker, A.4
-
5
-
-
0030682962
-
An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution
-
March
-
J. C. Chen, D. Sylvester, C. Hu, H. Aoki, S. Nakagawa, and S.-Y. Oh, "An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution," International Conference on Microelectronic Test Structures, pp. 77-80, March 1997.
-
(1997)
International Conference on Microelectronic Test Structures
, pp. 77-80
-
-
Chen, J.C.1
Sylvester, D.2
Hu, C.3
Aoki, H.4
Nakagawa, S.5
Oh, S.-Y.6
-
6
-
-
34548847570
-
-
private communication, Oct
-
R. Lefferts, private communication, Oct. 2003.
-
(2003)
-
-
Lefferts, R.1
-
7
-
-
34548848373
-
-
This extraction, and data shown in Figure 13, is a correction to the printed proceedings paper
-
This extraction, and data shown in Figure 13, is a correction to the printed proceedings paper.
-
-
-
-
8
-
-
0034453593
-
Threshold voltage extraction methods for MOS transistors
-
Oct
-
L. Dobrescu, M. Petrov, D. Dobrescu, and C. Ravariu, "Threshold voltage extraction methods for MOS transistors," CAS 2000 Proceedings of the International Semiconductor Conference, pp. 371-374, Oct. 2000.
-
(2000)
CAS 2000 Proceedings of the International Semiconductor Conference
, pp. 371-374
-
-
Dobrescu, L.1
Petrov, M.2
Dobrescu, D.3
Ravariu, C.4
-
9
-
-
0026138465
-
A simple MOSFET model for circuit analysis
-
Apr
-
T. Sakurai and A. R. Newton, "A simple MOSFET model for circuit analysis," IEEE Trans. an Electron Devices, Vol. 38, No. 4, pp. 887-894, Apr. 1991.
-
(1991)
IEEE Trans. an Electron Devices
, vol.38
, Issue.4
, pp. 887-894
-
-
Sakurai, T.1
Newton, A.R.2
-
10
-
-
0033325674
-
Ultra low capacitance measurements in multilevel metallisation CMOS by using a built-in electron-meter
-
Dec
-
B. Froment, F. Paillardet, M. Bely, I. Cluzel, E. Granger, M. Haond, and L. Dugoujon, "Ultra low capacitance measurements in multilevel metallisation CMOS by using a built-in electron-meter," International Electron Devices Meeting, pp. 897-900, Dec. 1999.
-
(1999)
International Electron Devices Meeting
, pp. 897-900
-
-
Froment, B.1
Paillardet, F.2
Bely, M.3
Cluzel, I.4
Granger, E.5
Haond, M.6
Dugoujon, L.7
-
11
-
-
0242359080
-
Charge-based on-chip measurement technique for the selective extraction of cross-coupling capacitances
-
May
-
A. Bogliolo, L. Vendrame, L. Bortesi, and E. Barachetti, "Charge-based on-chip measurement technique for the selective extraction of cross-coupling capacitances," IEEE Workshop on Signal Propagation on Interconnects, pp. 75-77, May 2002.
-
(2002)
IEEE Workshop on Signal Propagation on Interconnects
, pp. 75-77
-
-
Bogliolo, A.1
Vendrame, L.2
Bortesi, L.3
Barachetti, E.4
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