Dummy filling methods for reducing interconnect capacitance and number of fills

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2005, Pages 586-591

  Kurokawa, Atsushi ^a,b   Kanamoto, Toshiki ^c   Ibe, Tetsuya ^d   Kasebe, Akira ^e   Fong, Chang Wei ^f   Kage, Tetsuro ^g   Inoue, Yasuaki ^b   Masuda, Hiroo ^a  

^a STARC ^*  (Japan)

^b WASEDA UNIVERSITY   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

^d SANYO ELECTRIC CO LTD   (Japan)

^e Meitec Corp   (Japan)

^f Cristal Cosmotech Corp   (Japan)

^g TOKYO NATIONAL COLLEGE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DUMMY FILLINGS; FLOATING DUMMY; INTERCONNECT CAPACITANCE; ORDERS OF MAGNITUDE; PARALLEL LINE; PLANARIZATION; SIGNAL LINES; SYSTEM ON CHIP DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; METALS;

CAPACITANCE;

EID: 84886703433     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.47     Document Type: Conference Paper

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