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Volumn , Issue , 2006, Pages 691-696

Study of floating fill impact on interconnect capacitance

Author keywords

[No Author keywords available]

Indexed keywords

CLOSE PROXIMITY; CONFIGURATION PARAMETERS; COUPLING CAPACITANCE; EDGE EFFECT; INTERCONNECT CAPACITANCE; METAL DENSITY; PROCESS PARAMETERS;

EID: 84886738721     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.126     Document Type: Conference Paper
Times cited : (37)

References (11)
  • 1
    • 0033682012 scopus 로고    scopus 로고
    • An exhaustive method for characterizing the interconnect capacitance considering the floating dummy-fills by employing an efficient field solving algorithm in intl
    • J.-K. Park, K.-H. Lee, J.-H. Lee and Y.-K. Park. An Exhaustive Method for Characterizing the Interconnect Capacitance Considering the Floating Dummy-Fills by Employing an Efficient Field Solving Algorithm In Intl. Conf. on SISPAD, pages 98-101, 2000.
    • (2000) Conf. on SISPAD , pp. 98-101
    • Park, J.-K.1    Lee, K.-H.2    Lee, J.-H.3    Park, Y.-K.4
  • 2
    • 0003156497 scopus 로고
    • Chemical mechanical polishing of interlayer dielectric: A review
    • I. Ali, S. Roy and G. Shinn. Chemical Mechanical Polishing of Interlayer Dielectric: A Review. In Solid State Technol., volume 37, pages 63-70, 1994.
    • (1994) Solid State Technol , vol.37 , pp. 63-70
    • Ali, I.1    Roy, S.2    Shinn, G.3
  • 6
    • 0035716853 scopus 로고    scopus 로고
    • Analyzing the effects of floating dummy-fills: From feature scale analysis to full-chip rc extraction
    • K.-H. Lee, J.-K. Park, Y.-N. Yoon, D.-H. Jung, J.-P. Shin, Y.-K. Park and J. T Kong. Analyzing the Effects of Floating Dummy-Fills: From Feature Scale Analysis to Full-Chip RC Extraction. In IEDM Tech. Dig., pages 685-688, 2001.
    • (2001) IEDM Tech. Dig. , pp. 685-688
    • Lee, K.-H.1    Park, J.-K.2    Yoon, Y.-N.3    Jung, D.-H.4    Shin, J.-P.5    Park, Y.-K.6    Kong, J.T.7
  • 7
    • 84942123552 scopus 로고    scopus 로고
    • Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling
    • W.-S. Lee, K.-H. Lee, J.-K. Park, T.-K. Kim and Y.-K. Park. Investigation of the Capacitance Deviation due to Metal-Fills and the Effective Interconnect Geometry Modeling. In Intl. Symp. on Quality Electronic Design, page 354, 2003.
    • (2003) Intl. Symp. on Quality Electronic Design , pp. 354
    • Lee, W.-S.1    Lee, K.-H.2    Park, J.-K.3    Kim, T.-K.4    Park, Y.-K.5
  • 8
    • 0032028732 scopus 로고    scopus 로고
    • The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes
    • B. Stine, D. Boning, J. Chung and L. Camilletti. The Physical and Electrical Effects of Metal-fill Patterning Practices for Oxide Chemical-Mechanical Polishing Processes. In IEEE Trans. on Electron Devices, volume 45, pages 665-679, 1998.
    • (1998) IEEE Trans. on Electron Devices, Volume 45 , pp. 665-679
    • Stine, B.1    Boning, D.2    Chung, J.3    Camilletti, L.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.