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Volumn , Issue , 2003, Pages 53-56

Regular logic fabrics for a via patterned gate array (VPGA)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES; LOGIC PROGRAMMING; MASKS; MOSFET DEVICES; STATIC RANDOM ACCESS STORAGE; TABLE LOOKUP;

EID: 0242696159     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (31)

References (8)
  • 3
    • 0041691438 scopus 로고    scopus 로고
    • A via patterned gate array (VPGA)
    • Technical Reports Series of the CMU Center for Silicon System Implementation, No. CSSI 02-15, Mar
    • L. Pileggi, H. Schmit, J. Shah, Y. Tong, C. Patel, V. Chandra, "A Via Patterned Gate Array (VPGA)," Technical Reports Series of the CMU Center for Silicon System Implementation, No. CSSI 02-15, Mar 2002.
    • (2002)
    • Pileggi, L.1    Schmit, H.2    Shah, J.3    Tong, Y.4    Patel, C.5    Chandra, V.6
  • 4
    • 0041691437 scopus 로고    scopus 로고
    • Customizable and programmable cell array
    • US Patent 6,311,790, 18 Dec
    • Z. Or-Bach, Z. Wurman, R. Zeman, L. Cooke, "Customizable and programmable cell array," US Patent 6,311,790, 18 Dec 2001.
    • (2001)
    • Or-Bach, Z.1    Wurman, Z.2    Zeman, R.3    Cooke, L.4
  • 5
    • 0032646901 scopus 로고    scopus 로고
    • The design of a SRAM-based field-programmable gate array - Part II: Circuit design and layout
    • Sept
    • P. Chow, S.O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, "The design of a SRAM-based field-programmable gate array - part II: circuit design and layout," IEEE Trans. on VLSI Systems, Vol. 7, No. 3, Sept 1999, pp. 321-330.
    • (1999) IEEE Trans. on VLSI Systems , vol.7 , Issue.3 , pp. 321-330
    • Chow, P.1    Seo, S.O.2    Rose, J.3    Chung, K.4    Paez-Monzon, G.5    Rahardja, I.6
  • 7
    • 0031119401 scopus 로고    scopus 로고
    • Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems
    • Apr
    • F. S. Lai, W. Hwang, "Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems," IEEE Journal of Solid-State Circuits, Vol.32, No. 4, Apr 1997, pp. 563-573.
    • (1997) IEEE Journal of Solid-State Circuits , vol.32 , Issue.4 , pp. 563-573
    • Lai, F.S.1    Hwang, W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.