Performance and yield optimization of mm-wave PLL front-end in 65nm SOI CMOS

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

Volumn , Issue , 2007, Pages 525-528

  Lim, Daihyun ^a   Kim, Jonghae ^b   Plouchart, Jean Olivier ^b   Kim, Daeik ^b   Cho, Ongyeun ^b   Boning, Duane S ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b IBM   (United States)

Author keywords

Frequency divider; Inductive peaking; mm wave CMOS; Process variation; VCO

Indexed keywords

BANDWIDTH; BUFFER AMPLIFIERS; ENERGY DISSIPATION; FREQUENCY DIVIDING CIRCUITS; MILLIMETER WAVE DEVICES; VARIABLE FREQUENCY OSCILLATORS;

INDUCTIVE PEAKING; MM WAVE CMOS; PROCESS VARIATION;

PHASE LOCKED LOOPS;

EID: 34748878222     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RFIC.2007.380938     Document Type: Conference Paper

References (5)

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2. N. Fong, J. Kim, J.- O. Plouchart, N. Zamdmer, D. Liu, L. Wagner, C. Plett, G. Tarr, "A Low-Voltage 40-GHz Complementary VCO with 15% Frequency Tuning Range in SOI CMOS Technology," IEEE JSSC, vol. 39, no. 5, pp. 841-846, May 2004.
3. D. Lim, J. Kim, J.-O. Plouchart, C. Cho, D. Kim, R. Trzcinski, D. Boning, "Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS Technology," IEEE ISSCC, Feb. 2007.
4. U. Singh, M. M. Green, "Dynamics of high-frequency CMOS dividers," IEEE ISCAS, vol. 5, pp. 26-29, May 2002.
5. B. Razavi, "A Study of Injection Locking and Pulling in Oscillators," IEEE JSSC, vol. 39, no. 9, pp. 1415-1424, Sept. 2004.