A statistical algorithm for power- And timing-limited parametric yield optimization of large integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 10, 2007, Pages 1790-1802

  Mani, Muran ^b   Devgan, Anirudh ^a,c   Orshansky, Michael ^b   Zhan, Yaping ^d  

^a IEEE

^b The University of Texas at Austin   (United States)

^c MAGMA DESIGN AUTOMATION   (United States)

^d ADVANCED MICRO DEVICES   (United States)

Author keywords

Leakage; Manufacturability; Statistical optimization

Indexed keywords

BENCHMARKING; ELECTRIC POWER MEASUREMENT; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; OPTIMIZATION; PARAMETRIC AMPLIFIERS; POWER ELECTRONICS; STATISTICAL METHODS; THRESHOLD VOLTAGE;

BERKELEY PREDICTIVE TECHNOLOGY MODEL; LEAKAGE-POWER CONSUMPTION; PARAMETRIC YIELD LOSS; POWER MINIMIZATION; TIMING CONSTRAINTS;

INTEGRATED CIRCUITS;

EID: 34748850613     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2007.895797     Document Type: Article

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