Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages 617-624

  Chen, Chung Ping ^a   Chu, Chris C N ^a   Wong, D F ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONVERGENCE OF NUMERICAL METHODS; ITERATIVE METHODS; LAGRANGE MULTIPLIERS; LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION; PROBLEM SOLVING; RELAXATION PROCESSES; VLSI CIRCUITS;

DELAY MINIMIZATION; ELMORE DELAY MODEL; ONE-GATE/WIRE-AT-A-TIME LOCAL OPTIMIZATION;

COMPUTER AIDED LOGIC DESIGN;

EID: 0032318215     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/288548.289097     Document Type: Conference Paper

References (20)