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Volumn , Issue , 1998, Pages 617-624
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Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
CONVERGENCE OF NUMERICAL METHODS;
ITERATIVE METHODS;
LAGRANGE MULTIPLIERS;
LOGIC GATES;
MATHEMATICAL MODELS;
OPTIMIZATION;
PROBLEM SOLVING;
RELAXATION PROCESSES;
VLSI CIRCUITS;
DELAY MINIMIZATION;
ELMORE DELAY MODEL;
ONE-GATE/WIRE-AT-A-TIME LOCAL OPTIMIZATION;
COMPUTER AIDED LOGIC DESIGN;
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EID: 0032318215
PISSN: 10923152
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/288548.289097 Document Type: Conference Paper |
Times cited : (52)
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References (20)
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