Fast and exact transistor sizing based on iterative relaxation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 5, 2002, Pages 568-581

  Sundararajan, Vijay ^a,b   Sapatnekar, Sachin S ^a,c   Parhi, Keshab K ^a,c  

^a IEEE   (United States)

^b TEXAS INSTRUMENTS   (United States)

^c University of Minnesota   (United States)

Author keywords

Exact algorithms; Gate sizing; General convex delay models; Gradient descent; Iterative relaxation; Minimum cost network flow; Simple discrete monotonic programming; Speed of convergence; Transistor sizing

Indexed keywords

ITERATIVE RELAXATION; SIMPLE DISCRETE MONOTONIC PROGRAMMING; SOFTWARE PACKAGE MINFLOTRANSIT; TRANSISTOR SIZING;

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ITERATIVE METHODS; MATHEMATICAL PROGRAMMING; THEOREM PROVING; TRANSISTORS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036575359     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.998628     Document Type: Article

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