Static power optimization of deep submicron CMOS circuits for dual VT technology

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages 490-494

  Wang, Qi ^a   Vrudhula, Sarma B K ^a  

^a UNIVERSITY OF ARIZONA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED NETWORK ANALYSIS; DIGITAL INTEGRATED CIRCUITS; HEURISTIC METHODS; INTEGRATED CIRCUIT TESTING;

STATIC POWER OPTIMIZATION;

COMPUTER AIDED LOGIC DESIGN;

EID: 0032319165     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)