Modeling of variation in submicrometer CMOS ULSI technologies

IEEE Transactions on Electron Devices

Volumn 53, Issue 9, 2006, Pages 2168-2177

  Springer, Scott K ^a,b   Lee, Sungjae ^a,b   Lu, Ning ^b   Nowak, Edward J ^a,b   Plouchart, Jean Olivier ^a,b   Watts, Josef S ^a,b   Williams, Richard Q ^a,b   Zamdmer, Noah ^b  

^a IEEE   (United States)

^b IBM RESEARCH   (United States)

Author keywords

Integrated circuit modeling; Semiconductor device modeling; Semiconductor device variation; Semiconductor devices; Silicon on insulator (SOI) technology; Tolerance analysis

Indexed keywords

INTEGRATED CIRCUIT MODELING; LINEWIDTH VARIATION; SEMICONDUCTOR DEVICE MODELING; SEMICONDUCTOR DEVICE VARIATION; TOLERANCE ANALYSIS;

CIRCUIT SIMULATION; INTEGRATED CIRCUIT LAYOUT; POLYSILICON; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY; STATISTICAL METHODS;

CMOS INTEGRATED CIRCUITS;

EID: 33846269390     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.880165     Document Type: Article

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